Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
View Patent ↗A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.
1. A semiconductor device, comprising:
a gate electrode structure which comprises a gate electrode and a U-shaped dummy gate electrode substantially coplanar with said gate electrode,
wherein said dummy gate electrode is separated by a gap from said gate electrode and positioned outside of said gate electrode.
2. The semiconductor device as claimed in claim 1 , wherein said dummy gate electrode surrounds a majority of said gate electrode.
3. The semiconductor device as claimed in claim 1 , wherein said dummy gate electrode surrounds said gate electrode completely.
4. The semiconductor device as claimed in claim 1 , wherein said semiconductor device further includes a multi-layer structure comprising plural laminated layers which extend over said gate electrode structure, and surfaces of said plural laminated layers have grooves corresponding to said gap.
5. A semiconductor device, comprising:
a gate electrode structure which includes a gate electrode and a dummy gate electrode,
wherein said dummy gate electrode is separated by a gap from said gate electrode and positioned outside of said gate electrode, and
wherein said gate electrode is substantially circular with one flat side, said dummy gate electrode extends adjacent to and parallel to said flat side of said gate electrode.