Semiconductor integrated circuit device and a method of manufacturing the same
View Patent ↗A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
1. A semiconductor integrated circuit device comprising:
an active region having a substantially elliptical shape having a long axis and a short axis, a semiconductor element formed in said active region, a gate electrode which extends in a direction which is parallel to said short axis of said active region and across said active region, and a shallow groove isolation surrounding said active region,
wherein a peripheral portion of said active region is shaped in a form of a section that is rounded by round processing using a sidewall spacer as a mask.
wherein a sum of a size of the short axis of said active region and a width of said shallow groove isolation, in said direction which is parallel to the short axis of said active region, constitutes a minimum pitch,
wherein one-half of said minimum pitch is a minimum processing size determined according to a resolution limit of a photolithographic process used to form the semiconductor integrated circuit device, and
wherein the size of the short axis of said active region after removal of said sidewall spacer is set larger than one-half of said minimum pitch.
2. A semiconductor integrated circuit device according to claim 1 , wherein said semiconductor element constitutes a memory cell.
3. A semiconductor integrated circuit device according to claim 1 , wherein said gate constitutes a word line in a memory.
4. A semiconductor integrated circuit device according to claim 1 , wherein a thickness of a gate insulating film of said semiconductor element is equal in central and peripheral portions of said active region.
5. A semiconductor integrated circuit device according to claim 1 , wherein said semiconductor element formed in said active region is comprised of a MISFET.
6. A semiconductor integrated circuit device according to claim 5 , wherein said MISFET constitutes part of a memory cell in a DRAM.
7. A semiconductor integrated circuit device comprising:
a first active region having a substantially elliptical shape having a long axis and a short axis, a semiconductor element formed in said first active region, a gate electrode which extends in a direction which is parallel to said short axis of said first active region and across said first active region, a second active region being adjacent to said first active region in said direction which is parallel to the short side of said first active region and a shallow groove isolation formed between said first active region and said second active region:
wherein a peripheral portion of said first active region is shaped in a form of a section that is rounded by round processing using a sidewall spacer as a mask;
wherein a sum of a size of the short axis of said first active region and a width of a space defined between said first active region and said second active region, in said direction which is parallel to the short axis of said first active region, constitutes a minimum pitch;
wherein one-half of said minimum pitch is a minimum processing size determined according to a resolution limit of a photolithograihic process used to form the semiconductor integrated circuit device, and
wherein the size of the short axis of said first active region after removal of said sidewall spacer is set larger than one-half of said minimum pitch.
8. A semiconductor integrated circuit device according to claim 7 , wherein said semiconductor element constitutes a memory cell.
9. A semiconductor integrated circuit device according to claim 7 , wherein said gate constitutes a word line in a memory.
10. A semiconductor integrated circuit device according to claim 7 , wherein a peripheral portion of said first active region is shaped in a form of a section that is rounded and convex.
11. A semiconductor integrated circuit device according to claim 7 , wherein a thickness of a gate insulating film of said semiconductor element is equal in central and peripheral portions of said first active region.
12. A semiconductor integrated circuit device according to claim 7 , wherein said semiconductor element formed in said first active region is comprised of a MISFET.
13. A semiconductor integrated circuit device according to claim 12 , wherein said MISFET comprised part of a memory cell in a DRAM.