Method of repairing an integrated electronic circuit using a formed electrical isolation

1. A method of repairing an integrated electronic circuit, comprising the formation of an electrical isolation between two conducting parts of the circuit that are located at respective places of the circuit, a volume having been errantly hollowed out for the purpose of forming both at least one of the conducting parts and an electrical connection that connects the two places, the method comprising the following steps:

a) formation of a mask on the circuit having an aperture that reveals a portion of the errantly hollowed out volume;

b) deposition of an electrically insulating material on that portion revealed by the mask, so as to at least partly fill the errantly hollowed out volume; and

c) removal of the mask, so as to leave the errantly hollowed out volume at least partly filled with insulating material; and

d) depositing an electrically conducting material in a non-filled portion of the errantly hollowed out volume so as to form at least one of the two conducting parts electrically insulated from the other of the conducting parts by the deposited insulating material.

2. The method according to claim 1 , wherein the aperture in the mask is defined by directing an electron beam onto a part of the mask corresponding to said aperture.

3. The method according to claim 1 , wherein the insulating material present on the mask is removed at the same time as the mask during an operation of dissolving the mask in a liquid solution.

4. The method according to claim 1 , wherein the integrated electronic circuit is substantially planar and the electrical connection lies approximately perpendicular to the plane of the circuit.

5. The method according to claim 1 , wherein the integrated electronic circuit is substantially planar and the electrical connection is substantially parallel to the plane of the circuit.

6. The method according to claim 1 , wherein the electrically insulating material is deposited by sputtering.

7. The method according to claim 1 , wherein the electrically insulating material contains silicon atoms.

8. A method for integrated circuit repair during circuit fabrication, comprising:

using a fabrication mask which includes an error that produces both a volume for a conducting part of the circuit and an incorrect volume between two conducting parts of the circuit;

forming a mask having an aperture that reveals the incorrect volume;

forming an electrically insulating material block using the mask to at least partly fill the incorrect volume; and

depositing a metallization within the volume for the conducting part to form at least one of the two conducting parts, the formed electrically insulating material block insulating the two conducting parts from each other to correct for the error in the fabrication mask.

9. The method according to claim 8 , wherein the aperture in the mask is defined by directing an electron beam onto a part of the mask corresponding to said aperture.

10. The method according to claim 8 , wherein the incorrect volume extends vertically between two metallizations which form the two conducting parts.

11. The method according to claim 8 , wherein the incorrect volume extends horizontally along a single metallization which forms the two conducting parts.

12. A method for repairing an incorrectly lithography defined via location in an integrated circuit during fabrication, comprising:

forming a mask including an aperture exposing the via location above a first metallization and exposing a second metallization region above the via location;

depositing an insulator through the mask aperture to at least partly fill the via location with the insulator but not fill the second metallization region; and

forming a second metallization above the insulator in the second metallization region, the insulator correcting for the incorrectly defined via location and preventing electrical connection between the first and second metallizations.

13. A method for repairing an incorrectly lithography defined metallization location including two metallization segments in a metallization layer of an integrated circuit during fabrication, comprising:

forming a mask including an aperture exposing a portion of the incorrectly lithography defined metallization location;

filling the portion with an insulator deposited through the aperture in the mask; and

forming the metallization segments in the metallization layer with the insulator in the portion correcting for the incorrectly defined metallization location and preventing electrical connection between the two metallization segments.