IP Library Granted Patent US 6,897,075
Granted Patent B2
US 6,897,075 · App. 10/778,411 · Granted May 24, 2005

Method and apparatus for controlling photolithography overlay registration incorporating feedforward overlay information

Assignee: Advanced Micro Devices, Inc.
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Quick Facts
Patent No.
US 6,897,075
App. No.
10/778,411
Granted
May 24, 2005
Kind
B2
Abstract

A method for controlling a photolithography process includes forming a first layer on a selected wafer. A first overlay error associated with the first layer is measured. At least one parameter in an operating recipe for performing a photolithography process on a second layer formed on the first wafer is determined based on at least the first overlay error measurement. A processing line includes a photolithography stepper, and overlay metrology tool, and a controller. The photolithography stepper is configured to process wafers in accordance with an operating recipe. The overlay metrology tool is configured to measure overlay errors associated with the processing of the wafers in the photolithography stepper. The controller is configured to receive a first overlay error measurement associated with the formation of a first layer on a selected wafer and determine at least one parameter in the operating recipe for performing a photolithography process on a second layer formed on the selected wafer based on at least the first overlay error measurement.

Claims (30)

1. A processing line, comprising:

a photolithography stepper configured to process wafers in accordance with an operating recipe;

an overlay metrology tool configured to measure overlay errors associated with the processing of the wafers in the photolithography stepper; and

a controller configured to receive a first overlay error measurement associated with the formation of a first patterned layer on a selected wafer and determine at least one parameter in the operating recipe for performing a photolithography process on a second layer formed on the selected wafer based on at least the first overlay error measurement.

2. The processing line of claim 1 , wherein the photolithography tool further is further configured to perform the photolithography process on the second layer on the selected wafer based on the determined operating recipe.

3. The processing line of claim 1 , wherein the controller is further configured to implement a control thread associated with the performing of the photolithography process on the second layer for determining the at least one parameter.

4. The processing line of claim 1 , wherein the overlay metrology tool further comprises a review station.

5. The processing line of claim 1 , wherein the overlay metrology tool further comprises a scatterometry tool.

6. The processing line of claim 1 , wherein the at least one parameter further comprises at least one of an x-translation parameter, a y-translation parameter, an x-expansion wafer scale parameter, a y-expansion wafer scale parameter, a reticle magnification parameter, and a reticle rotation parameter.

7. A processing line, comprising:

a photolithography stepper configured to process wafers in accordance with an operating recipe;

an overlay metrology tool configured to measure overlay errors associated with the processing of the wafers in the photolithography stepper; and

a controller configured to receive a feedforward overlay error signal including a first overlay error measurement associated with the formation of a first patterned layer on a selected wafer, receive a feedback overlay error signal including a plurality of overlay error measurements associated with a photolithography process performed on a second layer on a plurality of wafers, and determine at least one parameter in the operating recipe for performing a photolithography process on the second layer on the selected wafer based on the feedforward overlay error signal and the feedback overlay error signal.

8. The processing line of claim 7 , wherein the photolithography tool further is further configured to perform the photolithography process on the second layer on the selected wafer based on the determined operating recipe.

9. The processing line of claim 7 , wherein the controller is further configured to implement a control thread associated with the performing of the photolithography process on the second layer for determining the at least one parameter.

10. The processing line of claim 7 , wherein the at least one parameter further comprises at one of an x-translation parameter, a y-translation parameter, an x-expansion wafer scale parameter, a y-expansion wafer scale parameter, a reticle magnification parameter, and a reticle rotation parameter.

11. The processing line of claim 7 , wherein the overlay metrology tool comprises an optical review station.

12. The processing line of claim 7 , wherein the overlay metrology tool comprises a scatterometry tool.

13. The processing line of claim 7 , wherein the second layer comprises a photoresist layer.

14. The processing line of claim 13 , wherein the photoresist layer comprises an exposed photoresist layer.

15. The processing line of claim 13 , wherein the photoresist layer comprises a developed photoresist layer.

16. A processing line, comprising:

means for forming a first patterned layer on a selected wafer;

means for measuring a first overlay error associated with the first layer; and

means for determining at least one parameter in an operating recipe for performing a photolithography process on a second layer formed on the first wafer based on at least the first overlay error measurement.

17. A processing line, comprising:

means for forming a first patterned layer on a selected wafer;

means for measuring a first overlay error associated with the first layer to generate a feedforward overlay error signal;

means for measuring a plurality of overlay errors associated with a process for performing a photolithography process on a second layer formed on a plurality of wafers to generate a feedback overlay error signal; and

means for determining at least one parameter in an operating recipe for forming the second layer on the selected wafer based on the feedforward overlay error signal and the feedback overlay error signal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2021
From: ADVANCED MICRO DEVICES, INC.
To: FULLBRITE CAPITAL PARTNERS
Reel/Frame 055766/0694 →
SECURITY INTEREST Recorded Apr 10, 2019
From: ADVANCED MICRO DEVICES, INC.
To: FULLBRITE CAPITAL PARTNERS, LLC
Reel/Frame 048844/0693 →
Continuity (2)
Division 1002248800 · Dec 17, 2001
Related Publication 20040159397A1 · Aug 19, 2004