Method and circuit for high speed transmission gate logic

1. A transmission logic gate circuit, comprising:

a passgate circuit having an input and an output;

a supply path coupled between a supply node and the output of the passgate circuit comprising a boosting transistor and an enabling transistor having a gate that receives an enable control signal; and

a boost path coupled between the input of the passgate and a gate of the boosting transistor that enables at least a portion of the supply path when a primary input signal at the input of the passgate circuit makes a predetermined transition.

2. The transmission logic gate circuit of claim 1 , wherein;

the passgate circuit comprises transistors of complementary conductivity having source drain paths arranged in parallel with one another.

3. The transmission logic gate circuit of claim 1 wherein:

the supply path comprises a pull-up path coupled between a high supply voltage and the output of the passgate circuit.

4. The transmission logic gate circuit of claim 1 , wherein:

the supply path comprises a pull-down path coupled between a low supply voltage and the output of the passgate circuit.

5. The transmission logic gate circuit of claim 1 , further including:

a logic gate having at least two inputs different than the passgate input and a gate output that provides the enable control signal.

6. The transmission logic gate circuit of claim 1 , wherein:

the boost path comprises at least one inverter configured having a switching point different than a potential midway between a high logic level and a low logic level of the primary input signal.

7. The transmission logic gate circuit of claim 6 , wherein:

the switching point is selected from the group consisting of a potential less than the midway potential and a potential greater than the midway potential.

8. The transmission logic gate circuit of claim 6 , wherein:

the inverter comprises complementary conductivity transistors having a gate width ratio of greater than 7:1.

9. The transmission logic gate circuit of claim 1 , further including:

a logic gate having at least two inputs different than the passgate input, and a logic gate output coupled to the supply path and an enable input of the passgate.

10. The transmission logic gate circuit of claim 9 , wherein:

the logic gate is selected from the group consisting of NAND gates and NOR gates.

11. A method of reducing propagation delay through a transmission gate logic circuit, comprising:

enabling a supply path coupled to an output of a passgate in advance of the activation of a primary signal at the input of the passgate; and

boosting a signal strength at the output of the passgate by allowing charge to flow through the supply path.

12. The method of claim 11 , wherein:

enabling the supply path includes enabling a pull up path coupled between the output of the passgate and a high power supply voltage; and

activation of the primary signal includes the primary signal transitioning from a low logic level to a high logic level while the passgate is enabled.

13. The method of claim 11 , wherein:

enabling the supply path includes enabling a pull-down path coupled between the output of the passgate and a low power supply voltage; and

activation of the primary signal includes the primary signal transitioning from a high logic level to a low logic level while the passgate is enabled.

14. The method of claim 11 , further including:

enabling the passgate according to at least one input signal that is different than the primary input signal.

15. A transmission gate logic circuit, comprising:

a passgate coupled between a primary signal input and a passgate output that is enabled according to logic values of at least one input signal that is different than the primary signal;

a supply path coupled between the passgate output and a first predetermined potential;

a boost path coupled between the primary signal input and the supply path that enables at least a first portion of the supply path in response to a predetermined transition in the primary signal; and

a logic circuit having inputs that receive the at least one input signal and a logic circuit output, at least a second portion of the supply path and the passgate being enabled in response to the logic circuit output having a first value.

16. The transmission gate logic circuit of claim 15 , wherein:

the passgate comprises at least one n-channel transistor;

the supply path includes at least one p-channel transistor having a source-drain path coupled between a high power supply voltage and the passgate output; and

the boost path includes an inverter including an n-channel transistor having a gate width greater than a p-channel transistor according to a ratio that is greater than 7:1.

17. The transmission gate logic circuit of claim 15 , wherein:

the passgate comprises at least one p-channel transistor;

the supply path includes at least one n-channel transistor having a source-drain path coupled between a low power supply voltage and the passgate output; and

the boost path includes an inverter including a p-channel transistor having a gate width greater than an n-channel transistor according to a ratio that is greater than 7:1.

18. The transmission gate logic circuit of claim 15 , further including:

a logic setting device coupled between the passgate output and a second predetermined potential that provides a current path when the logic circuit output has a second value.

19. The transmission gate logic circuit of claim 15 , further including:

an enable path coupled between the logic circuit output and the supply path that enables at least a second portion of the supply path in response to a predetermined output of the logic circuit.