IP Library Granted Patent US 7,539,190
Granted Patent B2
US 7,539,190 · App. 10/778,857 · Granted May 26, 2009

Multicasting in a shared address space

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Quick Facts
Patent No.
US 7,539,190
App. No.
10/778,857
Granted
May 26, 2009
Kind
B2
Abstract

There is disclosed apparatus and methods of multicasting in a shared address space. There may be defined a number of portions of the address space. There may be groups of the portions, and data units addressed to one portion within the group may be re-addressed to the other portions.

Claims (96)

1. A method of multicasting data units having destination addresses in a shared memory address space, comprising:

dividing the shared memory address space into a plurality of portions, wherein respective individual portions of the shared memory address space are associated with each of a plurality of ports of a switch, respective multicast portions are associated with at least some of the ports, and wherein the multicast portions have associations with one other

the method further comprising, for a given data unit:

if the destination address is in an individual portion associated with one of the ports, then forwarding the data unit for transmission out the associated port

if the destination address is in a first multicast portion associated with one of the ports, then

forwarding the data unit for transmission out the port associated with the first multicast portion

forwarding the data unit for transmission out a port associated with a second multicast portion associated with the first multicast portion, wherein the forwarded data unit is revised to specify a destination address within the second multicast portion,

transmitting data units through at least some of the ports via memory-mapped I/O into the shared memory address space.

2. The method of multicasting of claim 1 wherein the individual portions are unique within the shared memory address space with respect to one another.

3. The method of multicasting of claim 1 wherein the multicast portions are unique within the shared memory address space with respect to one another.

4. A switch for multicasting in a shared memory address space, the switch comprising

a buffer for storing data units, the data units having destination addresses in the shared memory address space

a first port associated with a first address portion in the shared memory address space, the first address portion including a first multicast address portion

a second port associated with a second address portion in the shared memory address space, the second address portion including a second multicast address portion associated with the first multicast address portion logic to

cause data units in the buffer having a destination address in the first multicast address portion to be forwarded for transmission out the first port without being removed from the buffer and then replace the destination address with an address in the second multicast address portion

cause data units in the buffer having a destination address in the second address portion to be forwarded for transmission out the second port,

wherein the switch has logic to transmit data units through the first port and the second port via memory-mapped I/O into the shared memory address space.

5. The switch for multicasting in a shared memory address space of claim 4 wherein

the first address portion has a first size

the second address portion has a second size

the second size is equal to the first size.

6. The switch for multicasting in a shared memory address space of claim 4 wherein

the first address portion has a first base address

the second address portion has a second base address

the first base address and the second base address differ by only a single digit.

7. The switch for multicasting in a shared memory address space of claim 4 having at least three ports, wherein the logic supports all of the ports having the characteristics defined for the first port.

8. The switch for multicasting in a shared memory address space of claim 4 wherein the logic is further to cause data units in the buffer having a destination address in the second portion to be forwarded for transmission out the second port and be removed from the buffer.

9. The switch for multicasting in a shared memory address space of claim 4

wherein the first address portion includes a first individual address portion

wherein the second address portion includes a second individual address portion

wherein the logic is further to

cause data units in the buffer having a destination address in the first individual address portion to be forwarded for transmission out the first port and be removed from the buffer

cause data units in the buffer having a destination address in the second individual address portion to be forwarded for transmission out the second port and be removed from the buffer.

10. The switch for multicasting in a shared memory address space of claim 9 wherein the first individual address portion comprises only a portion of the first address portion in the shared memory address space assigned to the first port.

11. A switch for multicasting in a shared memory address space, the switch comprising

a buffer

logic to store data units into the buffer

a first port associated with a first address portion in the shared memory address space, the first address portion including an individual portion and a multicast portion

a second port associated with a second address portion in the shared memory address space including an individual portion and a multicast portion logic to

cause data units in the buffer having a destination address in the individual portion of the first address portion to be forwarded for transmission out the first port and be removed from the buffer

cause data units in the buffer having a destination address in the individual portion of the second portion to be forwarded for transmission out the second port and be removed from the buffer

cause data units in the buffer having a destination address in the multicast portion of the first address portion to be forwarded for transmission out the first port without being removed from the buffer and then replace the destination address with an address in the multicast portion of the second address portion

cause data units in the buffer having a destination address in the multicast portion of the second portion to be forwarded for transmission out the second port,

wherein the switch has logic to transmit data units through the first port and the second port via memory-mapped I/O into the shared memory address space.

12. The switch for multicasting in a shared memory address space of claim 11 further comprising

a third port associated with a third address portion in the shared memory address space including an individual portion and a multicast portion logic to

cause data units in the buffer having a destination address in the individual portion of the third address portion to be forwarded for transmission out the third port and be removed from the buffer

replace the destination address of data units in the buffer having a destination address in the multicast portion of the second address portion with an address in the multicast portion of the third address portion

cause data units in the buffer having a destination address in the multicast portion of the third portion to be forwarded for transmission out the third port.

13. The switch for multicasting in a shared memory address space of claim 11 wherein

the multicast portion of the first address portion has a first size

the multicast portion of the second address portion has a second size

the second size is equal to the first size.

14. The switch for multicasting in a shared memory address space of claim 11 wherein

the multicast portion of the first address portion has a first base address

the multicast portion of the second address portion has a second base address

the first base address and the second base address differ by only a single digit.

15. The switch for multicasting in a shared memory address space of claim 11 having at least three ports, wherein the logic supports all of the ports having the characteristics defined for the first port.

16. The switch for multicasting in a shared memory address space of claim 11 wherein the logic is further to cause data units in the buffer having a destination address in the multicast portion of the second address portion to be forwarded for transmission out the second port and be removed from the buffer.

17. The switch for multicasting in a shared memory address space of claim 11 , wherein the first address portion includes a broadcast portion, and the second address portion includes a broadcast portion, the switch further comprising

a third port associated with a third address portion in the shared memory address space including an individual portion, a multicast portion and a broadcast portion logic to

cause data units in the buffer having a destination address in the individual portion of the third address portion to be forwarded for transmission out the third port and be removed from the buffer

cause data units in the buffer having a destination address in the broadcast portion of the first address portion, the second address portion or the third address portion to be forwarded for transmission out the first port, the second port and the third port with the destination address set to an address in the broadcast portion of the respective address portion for the respective port.

18. A method of multicasting in a shared memory address space using a switch having a buffer, a first port and a second port, the method comprising

associating a first address portion in the shared memory address space with the first port, the first address portion including an individual portion and a multicast portion

associating a second address portion in the shared memory address space with the second port, the second address portion including an individual portion and a multicast portion

storing data units in the buffer, the data units including a destination address in the shared memory address space

if a data unit in the buffer has a destination address in the individual portion of the first address portion, then

forwarding the data unit for transmission out the first port

removing the data unit from the buffer

if a data unit in the buffer has a destination address in the multicast portion of the first address portion, then

forwarding the data unit for transmission out the first port

replacing the destination address of the data unit with an address in the multicast portion of the second address portion

forwarding the data unit for transmission out the second port

removing the data unit from the buffer

if a data unit in the buffer has a destination address in the individual portion of the second address portion, then

forwarding the data unit for transmission out the second port

removing the data unit from the buffer

transmitting data units through the first port via memory-mapped I/O into the shared memory address space

transmitting data units through the second port via memory-mapped I/O into the shared memory address space.

19. The method of multicasting in a shared memory address space of claim 18 wherein

the multicast portion of the first address portion has a first size

the multicast portion of the second address portion has a second size

the second size is equal to the first size.

20. The method of multicasting in a shared memory address space of claim 18 , wherein there is a third port, the method further comprising providing characteristics defined for the first port for the second port and the third port.

21. The method of multicasting in a shared memory address space of claim 18 further comprising, if a data unit in the buffer has a destination address in the individual portion of the second address portion, then

forwarding the data unit for transmission out the second port

removing the data unit from the buffer.

22. The method of multicasting in a shared memory address space of claim 18 , wherein the first address portion includes a broadcast portion and the second address portion includes a broadcast portion, the method further comprising

associating a third address portion in the shared memory address space with a third port, the third address portion including an individual portion, a multicast portion and a broadcast portion

if a data unit in the buffer has a destination address in the individual portion of the third address portion, then

forwarding the data unit for transmission out the third port

removing the data unit from the buffer

if a data unit in the buffer has a destination address in the broadcast portion of the first address portion, the second address portion or the third address portion, then

forwarding the data unit for transmission out the first port, the second port and the third port with the destination address set to an address in the broadcast portion of the respective address portion for the respective port

removing the data unit from the buffer.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2015
From: INTERNET MACHINES LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036100/0113 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2011
From: TOPSIDE RESEARCH, LLC
To: INTERNET MACHINES MC, LLC
Reel/Frame 026024/0814 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2007
From: INTERNET MACHINES CORP.
To: TOPSIDE RESEARCH, LLC
Reel/Frame 019211/0612 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2004
From: STEWART, HEATH; DE LA GARRIGUE, MICHAEL; HAYWOOD, CHRIS; REINER, THOMAS; WONG, KEN
To: INTERNET MACHINES CORP.
Reel/Frame 014673/0459 →