Method and system for onboard bit error rate (BER) estimation in a port bypass controller
View Patent ↗Certain aspects of the method may comprise receiving via a first port of the port bypass controller, a data stream comprising at least one known bit pattern. Upon locking onto at least a portion of the known bit pattern in the received data stream, a bit error rate may be generated based on a bit-by-bit comparison of at least a portion of the data stream received after locking occurs. At least a portion of the data stream may be compared with a corresponding portion of expected data. The bit error rate may be calculated based on results from comparing at least a portion of the data stream with a corresponding portion of the expected data. The known bit pattern may be internally generated within the port bypass controller or it may be externally generated by a host system.
1. A method for bit error estimation in a port bypass controller, the method comprising:
receiving via a port of the port bypass controller, a data stream comprising at least one known bit pattern;
locking onto at least a portion of said known bit pattern in said received data stream; and
generating a bit error rate based on a bit-by-bit comparison of at least a portion of said data stream received after said locking onto at least a portion of said known bit pattern.
2. The method according to claim 1 , comprising comparing said at least a portion of said data stream with a corresponding portion of expected data.
3. The method according to claim 2 , comprising calculating said bit error rate based on results from said comparing of said at least a portion of said data stream with a corresponding portion of expected data.
4. The method according to claim 1 , wherein said at least one known bit pattern is internally generated within the port bypass controller.
5. The method according to claim 1 , wherein said at least one known bit pattern is externally generated by a host system.
6. The method according to claim 1 , comprising selecting said port of said port bypass controller prior to said receiving.
7. The method according to claim 6 , comprising transferring said data stream to said selected port of said port bypass controller.
8. The method according to claim 1 , wherein said data stream comprises standardized stress frame patterns.
9. The method according to claim 1 , wherein said data stream comprises a plurality of user defined transmission words.
10. The method according to claim 1 , wherein said data stream comprises a plurality of ordered set sequences.
11. A machine-readable storage having stored thereon, a computer program having at least one code section for bit error estimation in a port bypass controller, the at least one code section being executed by a machine for causing the machine to perform steps, comprising:
receiving via a port of the port bypass controller, a data stream comprising at least one known bit pattern;
locking onto at least a portion of said known bit pattern in said received data stream; and
generating a bit error rate based on a bit-by-bit comparison of at least a portion of said data stream received after said locking onto at least a portion of said known bit pattern.
12. The machine-readable storage according to claim 11 , comprising code for comparing said at least a portion of said data stream with a corresponding portion of expected data.
13. The machine-readable storage according to claim 12 , comprising code for calculating said bit error rate based on results from said comparing of said at least a portion of said data stream with a corresponding portion of expected data.
14. The machine-readable storage according to claim 11 , wherein said at least one known bit pattern is internally generated within the port bypass controller.
15. The machine-readable storage according to claim 11 , wherein said at least one known bit pattern is externally generated by a host system.
16. The machine-readable storage according to claim 11 , comprising code for selecting said port of said port bypass controller prior to said receiving.
17. The machine-readable storage according to claim 16 , comprising code for transferring said data stream to said selected port of said port bypass controller.
18. The machine-readable storage according to claim 11 , wherein said data stream comprises standardized stress frame patterns.
19. The machine-readable storage according to claim 11 , wherein said data stream comprises a plurality of user defined transmission words.
20. The machine-readable storage according to claim 11 , wherein said data stream comprises a plurality of ordered set sequences.
21. A system for bit error estimation in a port bypass controller, the system comprising:
a port of the port bypass controller that receives a data stream comprising at least one known bit pattern;
said port locks onto at least a portion of said known bit pattern in said received data stream; and
at least one processor generating a bit error rate based on a bit-by-bit comparison of at least a portion of said data stream received after said locking onto at least a portion of said known bit pattern.
22. The system according to claim 21 , wherein said at least one processor compares said at least a portion of said data stream with a corresponding portion of expected data.
23. The system according to claim 22 , wherein said at least one processor calculates said bit error rate based on results from said comparing of said at least a portion of said data stream with a corresponding portion of expected data.
24. The system according to claim 21 , wherein said at least one known bit pattern is internally generated within the port bypass controller.
25. The system according to claim 21 , wherein said at least one known bit pattern is externally generated by a host system.
26. The system according to claim 21 , wherein said at least one processor selects said port of said port bypass controller prior to said receiving.
27. The system according to claim 26 , wherein said at least one processor transfers said data stream to said selected port of said port bypass controller.
28. The system according to claim 21 , wherein said data stream comprises standardized stress frame patterns.
29. The system according to claim 21 , wherein said data stream comprises a plurality of user defined transmission words.
30. The system according to claim 21 , wherein said data stream comprises a plurality of ordered set sequences.
31. The system according to claim 21 , wherein said at least one processor is a host processor.