Method of manufacturing a semiconductor device having self-aligned contacts

1. A method for manufacturing a semiconductor device, comprising:

forming on a substrate a plurality of gate electrodes having offset nitride films and gate insulation films;

forming a silicon oxide layer so as to cover said substrate and said gate electrodes;

forming a lower side wall spacer precursor layer that is thinner than said gate electrodes by etching said silicon oxide layer;

forming a silicon nitride layer so as to cover said lower side wall spacer percursor layer;

successively etching said silicon nitride layer and said lower side wall spacer precursor layer so as to form side wall spacers having a structure consisting of upper side wall spacer wall spacer portions, said upper side wall spacer portions being formed of said silicon nitride layer remaining on upper side walls of said gate electrodes, and said lower side wall spacer portions being formed of said silicon oxide layer remaining on lower side walls of said gate electrodes;

forming an interlayer insulation film so as to cover said gate electrodes having said side wall spacers formed thereon; and

etching said interlayer insulation film to form self-aligned contact holes that go through said interlayer insulation film,

wherein said forming a plurality of gate electrodes comprises forming said gate electrodes so as to provide a dense region where said gate electrodes are densely gathered and a sparse region where said gate electrodes are more scattered, so that a film thickness of said silicon oxide layer in said dense region is greater than a film thickness of said silicon oxide layer in said sparse region,

the method further comprising performing chemical mechanical polishing to smooth out said silicon oxide layer, prior to said forming a lower side wall spacer percursor layer.

2. A method for manufacturing a semiconductor device according to claim 1 ,

wherein during said forming a silicon oxide layer, layer formation conditions are set so that spaces between said gate electrodes in said dense and sparse regions are filled in by said silicon oxide layer, and

wherein said forming a lower side wall spacer precursor layer comprises etching said silicon oxide layer so that film thickness of said silicon oxide layer between said gate electrodes in said dense region equal to film thickness of said silicon oxide layer between said gate electrodes in said sparse region.

3. A method for manufacturing a semiconductor device according to claim 2 ,

wherein said silicon oxide layer is formed using PSG, (phosphosilicate glass), BPSG (boron-phosphosilicate glass), P-TEOS.NSG (non-doped silicate glass by plasma CVD using tetraehylorthosilicate), P-SiH 4 .NSG (non-doped silicate glass by plasma CVD using silane).

4. A method for manufacturing a semiconductor device, comprising:

forming first and second gate electrodes on a substrate, wherein the first gate electrodes are formed in a first region with a first density, and the second gate electrodes are formed in a second region with a second density, the second density being lower than the first density;

forming a silicon oxide layer so as to cover the substrate and the first and second gate electrodes, a film thickness of said silicon oxide layer in the first region is greater than a film thickness of said silicon oxide layer in the second region;

performing chemical mechanical polishing to smooth out said silicon oxide layer;

forming a lower side wall spacer percursor layer that is thinner than the first and second gate electrodes by etching said silicon oxide layer, after said performing chemical mechanical polishing;

forming a silicon nitride layer so as to cover the lower side wall spacer percursor layer;

sucessively etching the silicon nitride layer and the lower side wall spacer percursor so as to form side wall spacers having a structure consisting of first and second upper side wall spacer portions and first and second lower side wall spacer portions, the first upper side wall spacer portions being formed of said silicon nitride layer on upper side walls of the first gate electrodes, the first lower side wall spacer portions being formed of said silicon oxide layer on lower side walls of the first gate electrodes, the second upper side wall spacer portions being formed of said silicon nitride layer on upper side walls of the second gate electrodes, and the second lower side wall spacer portions being formed of said silicon oxide layer on lower side walls of the second gate electrodes;

forming an interlayer insulation film so as to cover the gate electrodes having the side wall spacer portions formed thereon; and

etching the interlayer insulation film to thereby form self-aligned contact holes that go through said interlayer insulation film.

5. A method for manufacturing a semiconductor device according to claim 4 , wherein the silicon oxide layer is formed using phosphosilicate glass, boron-phosphosilicate glass, P-TEOS. non-doped silicate glass formed by plasma deposition using tetraehylorthosilicate, or P-SiH 4 .non-doped silicate glass formed by plasma deposition using silane glass.

6. A method for manufacturing a semiconductor device according to claim 4 , wherein during said forming a silicon oxide layer, layer formation conditions are set so that spaces between the first gate electrodes in the first region and spaces between the second gate electrodes in the second region are filled in by said silicon oxide layer, and

wherein said forming a lower side wall spacer percursor layer comprises etching said silicon oxide layer so that film thickness of said silicon oxide layer between the first gate electrodes is equal to film thickness of said silicon oxide layer between the second gate electrodes.