IP Library Granted Patent US 7,072,293
Granted Patent B2
US 7,072,293 · App. 10/780,111 · Granted Jul 4, 2006

Load sharing/trunking in a communication device

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Quick Facts
Patent No.
US 7,072,293
App. No.
10/780,111
Granted
Jul 4, 2006
Kind
B2
Abstract

A method and apparatus is described which pertains to load sharing/trunking in a communication device used in unicast and/or multicasting interchange of information. A plurality of available ports in the interface cards of the device is identified. More than one port is selected to be configured as a Multi-Link Trunk (MLT) even through the ports may be located on different interface cards.

Claims (50)

1. A method comprising:

identifying a Multi-Link Trunk (MLT) in which data is to be transmitted;

identifying a plurality of ports included in the MLT;

generating an identification for the data to be transmitted, the identification based on a data packet's source address and destination address, and wherein the identification is pseudo-random for different source-dest pairs and same for same source-dest pairs; and

using the identification to determine a physical port in which the data is to be transmitted in the MLT.

2. The method of claim 1 , wherein generating the identification further comprises:

generating the identification using a random generator.

3. The method of claim 1 , further comprising:

selecting a portion of at least a source address and a destination address of the data on which Exclusive—OR (XOR) operation is performed to generate the identification.

4. The method of claim 1 , wherein using the identification to determine a physical port further comprises:

determining a number of ports in the MLT;

using the number of ports as a base for a modulus (MOD) function;

performing the MOD functions on the identification; and

using a result of the MOD function as an index to select one of the ports in said MLT.

5. A processor readable medium which when executed by a processor causes the processor to perform a method comprising:

identifying a Multi-Link Trunk (MLT) in which data is to be transmitted;

identifying a plurality of ports included in the MLT;

generating an identification for the data to be transmitted, the identification based on a data packet's source address and destination address, and wherein the identification is pseudo-random for different source-dest Dairs and same for same source-dest pairs; and

using the identification to determine a physical port in which the data is to be transmitted in the MLT.

6. A processor readable medium as in claim 5 , wherein generating the identification further comprises:

generating the identification using a random generator.

7. The processor readable medium of claim 5 , further comprising:

selecting a portion of at least a source address and a destination address of the data on which Exclusive-OR (XOR) function is performed to generate the identification.

8. The processor readable medium of claim 5 , wherein using the identification to determine a physical port further comprises:

determining a number of ports in the MLT;

using the number of ports as a base for a modulus (MOD) function;

performing the MOD function on the identification; and

using a result of the MOD function as an index to select one of the ports in the MLT.

9. A method comprising:

identifying a plurality of ports available in a plurality of interface cards in a device; and

selecting a grouping of ports of the plurality of ports as a Multi-Link Trunk (MLT), at least one port of the grouping of ports is located in an interface card separate from another port of the grouping of ports which is located in another interface card, and wherein the grouping of ports includes two of the plurality of ports, and selecting the grouping of ports further comprises selecting the ports that are secure.

10. An apparatus comprising:

a first circuit to identify a plurality of ports available in a plurality of interface cards in a device;

a second circuit to select a grouping of ports of the plurality of ports as a Multi-Link Trunk (MLT), at least one port of the grouping of ports is located in an interface card separate from another port of the grouping of ports which is located in another interface card; and

a third circuit to determine if a port included in an MLT has failed;

a fourth circuit to select another port from the identified plurality of ports; and

a fifth circuit to replace the failed port with the selected port.

11. An apparatus comprising:

a first circuit to identify a plurality of ports available in a plurality of interface cards in a device;

a second circuit to select a grouping of ports of the plurality of ports as a Multi-Link Trunk (MLT), at least one port of the grouping of ports is located in an interface card separate from another port of the grouping of ports which is located in another interface card; and

a third circuit to select the grouping of ports that are secure.

12. A processor readable medium which when executed by a processor causes the processor to perform a method comprising:

identifying a plurality of ports available in a plurality of interface cards in a device;

selecting a grouping of ports of the plurality of ports as a Multi-Link Trunk (MLT), at least one port of the grouping of ports is located in an interface card separate from another port of the grouping of ports which is located in another interface card;

determining if a port included in an MLT has failed;

selecting another port from the identified plurality of ports; and

replacing the failed port with the selected port.

13. A processor readable medium which when executed by a processor causes the processor to perform a method comprising:

identifying a plurality of ports available in a plurality of interface cards in a device; and

selecting a grouping of ports of the plurality of ports as a Multi-Link Trunk (MLT), at least one port of the grouping of ports is located in an interface card separate from another port of the grouping of ports which is located in another interface card, and wherein selecting the grouping of ports further comprises selecting the ports which are secure.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 48612/0598) Recorded May 18, 2023
From: GOLDMAN SACHS BANK USA., AS COLLATERAL AGENT
To: AVAYA INC.; INTELLISIST, INC.; AVAYA INTEGRATED CABINET SOLUTIONS LLC; OCTEL COMMUNICATIONS LLC; VPNET TECHNOLOGIES, INC.; ZANG, INC. (FORMER NAME OF AVAYA CLOUD INC.); HYPERQUALITY, INC.; HYPERQUALITY II, LLC; CAAS TECHNOLOGIES, LLC; AVAYA MANAGEMENT L.P.
Reel/Frame 063691/0294 →
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 48612/FRAME 0582 Recorded Apr 26, 2023
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: AVAYA HOLDINGS CORP.; AVAYA INC.; AVAYA MANAGEMENT L.P.
Reel/Frame 063456/0428 →
SECURITY INTEREST Recorded Mar 15, 2019
From: AVAYA MANAGEMENT L.P.
To: CITIBANK, N.A.
Reel/Frame 048612/0582 →
SECURITY INTEREST Recorded Mar 15, 2019
From: AVAYA MANAGEMENT L.P.
To: GOLDMAN SACHS BANK USA
Reel/Frame 048612/0598 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2019
From: AVAYA HOLDINGS LIMITED
To: AVAYA MANAGEMENT L.P.
Reel/Frame 048577/0492 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2010
From: NORTEL NETWORKS LIMITED
To: AVAYA HOLDINGS LIMITED
Reel/Frame 023998/0799 →