Computer architecture and system for efficient management of bi-directional bus
View Patent ↗An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular, by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.
1. A system for managing bi-directional bus usage, comprising:
a bi-directional bus;
a read queue for pending read bus transactions;
a write queue for pending write bus transactions;
a mux having a first input coupled to said read queue and a second input coupled to said write queue and an output coupled to said bus:
bus streaming control logic coupled to said read queue and said write queue having at least one control signal coupled to said mux; and
wherein said bus streaming control logic selects for issuance to the bus either read transactions from said read queue or write transactions from said write queue to reduce the number of transitions between read transactions and write transactions.
2. The system of claim 1 wherein said bus streaming control logic selectively controls the mix to stream either read transactions together from said read queue or write transactions together from said write queue to said bus to reduce the number of transitions between read transactions and write transactions.
3. The system of claim 1 wherein said bus streaming control logic uses a first control signal and a second control signal to selectively control the mux to output either read transactions from said read queue or write transactions from said write queue to said bus.
4. The system of claim 3 wherein said bus streaming control logic asserts said first control signal to said mux in order to stop said read transactions from said read queue to said bus.
5. The system of claim 3 wherein said bus streaming control logic asserts said second control signal to said mux in order to stop said write transactions from said write queue to said bus.
6. The system of claim 1 wherein said bus streaming control logic further comprises a counter to track the number of pending write transactions in said write queue, and said bus streaming control logic transitions from write transactions to read transactions when said counter reaches a threshold value.
7. The system of claim 1 wherein said bus streaming control logic further comprises a counter to track the number of pending read transactions in said read queue, and said bus streaming control logic transitions from read transactions to write transactions when said counter reaches a threshold value.
8. A method, comprising:
tracking the number of pending writes in a write queue;
tracking the number of pending reads in a read queue;
tracking the number of consecutively issued reads when the number of pending writes reaches a pending write threshold;
tracking the number of consecutively issued writes when the number of pending reads reaches a pending read threshold;
transitioning from issuance of reads to issuance of writes when the number of pending writes reaches said pending write threshold and the number of consecutively issued reads reaches a consecutively issued read threshold; and
transitioning from issuance of writes to issuance of reads when the number of pending reads reaches said pending read threshold and the number of consecutively issued writes reaches a consecutively issued write threshold.
9. The method of claim 8 wherein transitioning from issuance of reads to issuance of writes comprises ceasing issuance of reads, waiting for a period of time, and then beginning to issue writes after said period of time.
10. The method of claim 8 wherein transitioning from issuance of writes to issuance of reads comprises ceasing issuance of writes, waiting for a period of time, and then beginning to issue reads after said period of time.
11. A system, comprising:
a bus;
a read queue configured to contain pending read transactions;
a write queue configured to contain pending write transactions; and
control logic configured to select for issuance to the bus either read transactions from said read queue or write transactions from said write queue to reduce the number of transitions between read transactions and write transactions.
12. The system of claim 11 wherein said control logic comprises a counter to track the number of pending write transactions in said write queue, and said control logic transitions from causing write transactions to be issued to causing read transactions to be issued when said counter reaches a threshold value.
13. The system of claim 11 wherein said control logic comprises a counter to track the number of pending read transactions in said read queue, and said control logic transitions from causing read transactions to be issued to causing issuing write transactions to be issued when said counter reaches a threshold value.