Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM
View Patent ↗An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective pair of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.
1. A method for reading data from a synchronous memory of the type having data cells arranged in rows and columns, comprising:
arranging said synchronous memory in a symmetrical layout along a horizontal direction to include:
a left plurality of N memory portions including a left memory block, a central sense amplifier block, and a right memory block arranged along said horizontal direction;
one centrally located single row cache;
a secondary sense amplifier block co-located with said centrally located single row cache; and
a right plurality of N memory portions including a left memory block, a central sense amplifier block, and a right memory block arranged along said horizontal direction, said single row cache disposed between said left plurality of memory portions and said right plurality of memory portions,
wherein N is at least equal to two;
receiving an initial command that is not a “read” command and receiving row address data for reading contents of a row of said synchronous memory selected by said row address data, said initial command exclusive of colunm address data;
moving said contents of said row into said single row cache;
after said contents of said row have been moved into said single row cache, receiving a “read” command and column address data; and
in response to said “read” command, reading data from said single row cache at a column address specified by said column address data for output by said synchronous memory.
2. The method of claim 1 wherein said initial command is received substantially concurrently with said row address data.
3. The method of claim 1 wherein said “read” command and said column address data are received substantially concurrently.
4. The method of claim 1 further comprising moving data read from said single row cache to an output of said synchronous memory after a predetermined number of clock cycles after said “read” command.
5. The method of claim 4 wherein moving said data read from said row cache to an output of said synchronous memory after a predetermined number of clock cycles comprises moving said data read from said single row cache to an output of said memory after two clock cycles.
6. The method of claim 4 wherein said predetermined number of clock cycles is two.
7. The method of claim 1 wherein said receiving an initial command comprises receiving a “bank activate” command.
8. The method of claim 1 further comprising performing a first precharging operation prior to receiving said initial command.
9. The method of claim 4 further comprising initiating a memory operation after said contents of said row have been moved into said single row cache and before said data read from said single row cache has been moved to said output of said synchronous memory.
10. The method of claim 9 wherein said memory operation comprises a precharging operation.
11. The method of claim 9 wherein said synchronous memory comprises a SDRAM array.