Serial line circuit, an apparatus implemented with a serial line circuit, and method thereof
View Patent ↗In one embodiment, the invention relates to a serial line circuit that comprises a serial information (SI) bus and at most two isolators interposed between a pair of programmable devices. In the TRANSMIT direction, a first programmable device is configured to multiplex serial data received from a plurality of serial UARTs and to route such data to the second programmable device over the SI bus and through a first isolator. In the RECEIVE direction, the second programmable device is configured to sample data from a plurality of serial interconnects and to route the sampled data to the first programmable device. The sampled data is routed over the SI bus and through a second isolator. The data transmission over the SI bus is in accordance with a proprietary serial transmission protocol described below.
1. A serial line circuit comprising:
a bus;
a plurality of isolators interposed between two portions of the bus;
a first component coupled to the bus, the first component to transfer information via a first isolator of the plurality of isolators, the first component is a programmable component being a field programmable gate array (FPGA) to multiplex serial data and to transfer the serial data over the bus via the first isolator; and
a second component coupled to the bus, the second component to transfer sampled information over the bus via a second isolator of the plurality of isolators.
2. The serial line circuit of claim 1 , wherein the second component is a programmable component being a complex programmable logic device (CPLD) that samples data from a plurality of serial connectors and routes the sampled data over the bus via the second isolator.
3. A serial line circuit comprising:
a bus;
a plurality of isolators interposed between two portions of the bus;
a first component coupled to the bus, the first component to transfer information via a first isolator of the plurality of isolators; and
a second component coupled to the bus, the second component to transfer sampled information over the bus via a second isolator of the plurality of isolators, the first component to receive serial data bits, multiplex the received serial data bits by forming data frames each including a plurality of overhead bits along with a serial bit of the received serial data bits, and to transfer the overhead bits along with the serial bit to the second component over the bus via the first isolator, the overhead bits including a serial port number to identify a serial line connector to receive the serial bit corresponding to the overhead bits.
4. The serial line circuit of claim 3 , wherein the first component receives the serial data bits from a plurality of serial Universal Asynchronous Receiver Transmitters (UARTs).
5. The serial line circuit of claim 3 , wherein the overhead bits include a valid bit to identify whether the serial bit is valid.
6. The serial line circuit of claim 3 , wherein the second component to receive a first data frame and to transfer a serial bit of the first data frame to a serial line connector determined by the serial port number contained in the overhead bits.
7. An electronic device comprising:
a plurality of serial port connectors; and
a serial line circuit coupled to the plurality of serial port connectors, the serial line circuit comprises
a first programmable component,
a second programmable component in communication with the plurality of serial port connectors,
a bus coupled to the first programmable component and the second programmable component,
a first isolator situated along the bus, the first isolator to receive a serial data bit preceded by control information from the first programmable component for transfer to the second programmable component, and
a second isolator situated along the bus, the second isolator to receive a sampled data bit preceded by control information from the second programmable component for transfer to the first programmable component,
wherein the first programmable component of the serial line circuit comprises a field programmable gate array (FPGA) to multiplex serial data received from a plurality of serial Universal Asynchronous Receiver Transmitters (UARTs) and to transfer at least the control information and the serial data bit of the serial data over the bus via the first isolator.
8. The electronic device of claim 7 , wherein the second programmable component of the serial line circuit comprises a complex programmable logic device (CPLD) that samples data from the plurality of serial port connectors and routes the sampled data over the bus via the second isolator.
9. An electronic device comprising:
a plurality of serial port connectors; and
a serial line circuit coupled to the plurality of serial port connectors, the serial line circuit comprises
a first programmable component,
a second programmable component in communication with the plurality of serial port connectors,
a bus coupled to the first programmable component and the second programmable component,
a first isolator situated along the bus, the first isolator to receive a serial data bit preceded by control information from the first programmable component for transfer to the second programmable component, and
a second isolator situated along the bus, the second isolator to receive a sampled data bit preceded by control information from the second programmable component for transfer to the first programmable component,
wherein the first programmable component of the serial line circuit to receive serial data bits including the serial data bit, to multiplex the received serial data bits by forming data frames, one of the data frames including a serial port number along with the serial data bit, and to transfer the serial port number along with the serial data bit to the second programmable component over the bus via the first isolator.
10. The electronic device of claim 9 , wherein the one of the data frames formed by the first programmable component further comprises a valid bit to identify whether the serial data bit is valid.
11. The electronic device of claim 9 , wherein the second programmable component to receive one of the data frames and to transfer the serial data bit to a first serial port connector of the plurality of serial port connectors determined by the serial port number.
12. A method comprising:
receiving a plurality of serial data bits;
multiplexing the plurality of serial data bits in order to transfer the serial data bits over an interconnect through a single isolator, the multiplexing comprises generating control information for each serial data bit of the plurality of data bits and transferring the control information along with a corresponding serial data bit immediately after each other, and a transmission rate of the interconnect exceeds a transmission rate of at least one interconnect providing the corresponding serial data bit by a factor of at least one-hundred;
recovering each of the plurality of serial data bits; and
determining a serial port connector for each of the plurality of serial data bits for routing to the serial port connector.
13. The method of claim 12 , wherein the control information comprises a serial port number.
14. The method of claim 13 , wherein the control information further comprises a valid bit to identify whether the corresponding serial data bit is valid.