Dry etching process for compound semiconductors
View Patent ↗Accordingly, this invention relates to an dry etching process for semiconductor wafers. More particularly, the present invention discloses a dry etching process including a halogen etchant ( 24 ) and a nitrogen gas ( 28 ) that selectively etches a compound semiconductor material ( 18 ) faster than the front-side metal layers ( 16 A)( 16 B). Further, the dry etching process produces a vertical wall profile on compound semiconductor material ( 18 ) in both X ( 38 ) and Y ( 40 ) crystalline directions without undercutting the top of a via-opening.
1. A dry etching process for a semiconductor wafer having variable thickness comprising the steps of:
placing in a chamber said semiconductor wafer having on one side a compound semiconductor material with an exposed portion and on the opposing side a metal layer;
releasing an halogen etchant into said chamber;
adding a nitrogen gas to said chamber;
heating said compound semiconductor material;
applying pressure to said halogen etchant and said nitrogen gas;
applying a bias power and a pulse-modulated power to said halogen etchant and said nitrogen gas; and
continuing the dry etching process until a desired via-hole is selectively etched in the compound semiconductor material to produce vertical sidewalls in X and Y crystalline directions therein without punch-through of the metal layer.
2. A dry etching process as recited in claim 1 wherein said compound semiconductor material has an etch rate that is within a range of approximately 70 times to approximately 80 times faster than said etch rate of a front-side metal layer on said compound semiconductor material.
3. A dry etching process as recited in claim 1 , wherein said chamber contains by volume not less than 10 parts halogen etchant to 1 part said nitrogen gas.
4. A dry etching process as recited in claim 3 , wherein said halogen etchant is one selected from the group consisting of Chlorine, Fluorine and Bromine.
5. A dry etching process as recited in claim 3 , wherein said halogen etchant is one selected from the group consisting of Hydrogen Bromide and Hydrogen Iodide.
6. A dry etching process as recited in claim 1 , wherein said halogen etchant is Hydrogen Bromide.
7. A dry etching process as recited in claim 1 , wherein said compound semiconductor material is selected from a group consisting of Gallium Arsenide and Indium Phosphide.
8. A dry etching process as recited in claim 1 , wherein said volume ratio of said halogen etchant to said nitrogen gas is selected from a range of approximately 10:1 to approximately 13:1.
9. A dry etching process as recited in claim 1 , wherein said heating step comprises applying a temperature to said halogen etchant and said nitrogen gas selected from a range of approximately 130 degrees C. to approximately 170 degrees C.
10. A dry etching process as recited in claim 1 , wherein applied pressure of said halogen etchant and said nitrogen gas is selected from a range of approximately 5 milli-Torr to approximately 20 milli-Torr.
11. A dry etching process as recited in claim 1 , wherein said bias power step comprises introducing a bias power to said semiconductor material selected from a range of approximately 20 Watts to approximately 50 Watts.
12. A dry etching process as recited in claim 1 , wherein said pulse-modulated power step comprises applying an inductively coupled plasma power to said compound semiconductor material selected from a range of approximately 350 Watts to approximately 750 Watts.
13. A dry etching process as recited in claim 1 , wherein a non-exposed portion of said semiconductor wafer is not damaged during said etching process.
14. A dry etching process as recited in claim 1 , wherein said addition of said nitrogen gas to said halogen etchant reduces said etch rate of said front-side metal layer by more than 90 percent.
15. A dry etching process for a semiconductor wafer comprising the steps of:
placing in a chamber said semiconductor wafer having on one side a compound semiconductor material with an exposed portion and on the opposing side a metal layer;
releasing a halogen etchant into said chamber;
adding nitrogen gas to said chamber;
heating said compound semiconductor material;
applying a bias power and an inductively coupled plasma power to said halogen etchant and said nitrogen gas; and
continuing the dry etching process until the desired via-hole is selectively etched in the compound semiconductor material;
thereby producing vertical sidewalls in X and Y crystalline directions for a compound semiconductor material having a variable thickness without punch-through of the metal layer.
16. The method of claim 15 wherein said dry etch process has an etch rate within a range of approximately 70 times to approximately 80 times faster than said etch rate of a front-side metal layer disposed on said compound semiconductor material.
17. The method of claim 15 wherein said halogen etchant to said nitrogen gas volume ratio is selected from a range of approximately 10:1 to approximately 12:1.