Structures and methods for fabricating vertically integrated HBT/FET device
View Patent ↗Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
1. A structure comprising:
a first epitaxial structure on top of the substrate, the epitaxial structure forming a portion of a FET;
a second epitaxial structure on top of the first epitaxial structure, the second epitaxial structure being shared by a HBT and the FET; and
a third epitaxial structure on top of the second epitaxial structure, the epitaxial structure forming a portion of the HBT.
2. The structure of claim 1 , wherein the second epitaxial structure further comprises a contact layer, said contact layer serving as both a cap layer for the FET and a subcollector layer for the HBT.
3. The structure of claim 2 , wherein the contact layer is highly doped.
4. The structure of claim 3 , wherein the contact layer is a n-type GaAs layer having a doping concentration of approximately 4.0×1018 cm −3 or more.
5. The structure of claim 2 , wherein a thickness of the contact layer is determined based on one or more design trade-offs between the HBT and the FET.
6. The structure of claim 2 , wherein a thickness of the contact layer is about 350 nm.
7. The structure of claim 1 , wherein the first epitaxial structure further comprises a low leakage buffer layer.
8. The structure of claim 7 , wherein the low leakage buffer layer further comprises one or more undoped GaAs or AIGaAs layers.
9. The structure of claim 1 , wherein the first epitaxial structure further comprises a set of MESFET epitaxial layers.
10. The structure of claim 9 , wherein the set of MESFET epitaxial layers further comprises an undoped GaAs spacer layer and a doped GaAs channel layer.
11. The structure of claim 1 , wherein the first epitaxial structure further comprises a set of pHEMT epitaxial layers.
12. The structure of claim 11 , wherein the set of pHEMT epitaxial layers further comprises a lower GaAs barrier layer, an lnGaAs channel layer and an AIGaAs or InGaP Schottky barrier layer.
13. The structure of claim 1 , wherein the third epitaxial structure further comprises a GaAs collector layer, a GaAs base layer and a InGaP emitter layer.