IP Library Granted Patent US 7,199,055
Granted Patent B2
US 7,199,055 · App. 10/786,440 · Granted Apr 3, 2007

Magnetic memory cell junction and method for forming a magnetic memory cell junction

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Quick Facts
Patent No.
US 7,199,055
App. No.
10/786,440
Granted
Apr 3, 2007
Kind
B2
Abstract

A method for patterning a magnetic memory cell junction is provided herein, which includes etching exposed portions of a stack of layers to a level spaced above a tunneling barrier layer of the stack of layers. In addition, the method may include implanting dopants into exposed portions of the stack of layers. For example, the method may include oxidizing and/or nitriding the exposed portions of the stack of layers. In some embodiments, the steps of etching and implanting dopants may form an upper portion of the magnetic cell junction. Alternatively, the method may include alternating the steps of etching and implanting dopants throughout the thickness of the exposed portions of the stack of layers. In either case, the stack of layers may include a magnetic layer which includes a material adapted to prevent the introduction of dopants underlying the tunneling barrier layer during the step of implanting.

Claims (34)

1. A method for forming a magnetic memory cell junction, comprising:

patterning a mask layer above a stack of layers;

etching exposed portions of the stack of layers;

terminating the step of etching at a level spaced above a tunneling barrier layer of the stack of layers and below a masked upper surface of a magnetic layer within the stack of layers; and

implanting dopants into remaining portions of the stack of layers arranged above the tunneling barrier layer.

2. The method of claim 1 , wherein the step of etching comprises etching between approximately 20% and approximately 95% of a thickness of the stack of layers arranged above the tunneling barrier layer.

3. The method of claim 1 , wherein the step of implanting comprises oxidizing the remaining portions of the stack of layers arranged above the tunneling barrier layer.

4. The method of claim 1 , wherein the step of implanting comprises nitriding the remaining portions of the stack of layers arranged above the tunneling barrier layer.

5. The method of claim 1 , wherein the step of implanting is adapted to prevent the introduction of dopants into portions of the stack of layers underlying the tunneling barrier layer.

6. The method of claim 1 , wherein a different magnetic layer of the stack of layers underlying the tunneling barrier layer comprises a material adapted to prevent the introduction of dopants within the different magnetic layer during the step of implanting.

7. A method for forming a magnetic memory cell junction, comprising:

patterning a mask layer above a stack of layers comprising a magnetic layer; and

alternately etching and implanting dopants into exposed portions of the stack of layers, wherein the step of alternately etching and implanting dopants comprises alternately etching and implanting dopants into exposed portions of the magnetic layer.

8. The method of claim 7 , wherein the step of alternately etching and implanting comprises:

generating veils along sidewalls of the patterned stack of layers; and

implanting dopants into the veils.

9. The method of claim 8 , wherein the step of alternately etching and implanting further comprises removing the doped veils.

10. The method of claim 7 , wherein the step of alternately etching and implanting comprises etching a greater amount of the stack of layers than the amount of the stack of layers implanted with dopants during the step of implanting.

11. The method of claim 7 , wherein the step of alternately etching and implanting comprises oxidizing the exposed portions of the stack of layers.

12. The method of claim 10 , wherein the step of alternately etching and implanting further comprises nitriding the exposed portions of the stack of layers.

13. The method of claim 7 , wherein the step of alternately etching and implanting is initiated with etching exposed portions of the stack of layers.

14. The method of claim 7 , wherein the step of alternately etching and implanting is initiated with implanting dopants into exposed portions of the stack of layers.

15. A method for forming a magnetic memory cell junction, comprising:

patterning a mask layer above a stack of layers;

etching exposed portions of the stack of layers in alignment with the mask layer, wherein the step of etching comprises generating veils along sidewalls of the patterned stack of layers;

implanting dopants into the veils; and

reiterating the steps of etching and implanting.

16. The method of claim 15 , wherein the step of reiterating the step of etching comprises removing doped veils and generating new veils.

17. The method of claim 15 , wherein the step of reiterating the step of etching comprises etching a greater amount of the stack of layers than the amount of the stack of layers implanted with dopants during the step of implanting.

18. The method of claim 15 , wherein the step of implanting comprises at least one of:

oxidizing the exposed portions of the stack of layers; and

nitriding the exposed port ions of the stack of layers.

19. The method of claim 7 , wherein the step of alternately etching and implanting further comprises alternately etching and implanting dopants into a tunnel barrier layer of the stack of layers.

20. The method of claim 15 , wherein the step of reiterating the steps of etching and implanting comprises repeating the steps of etching and implanting through a first set of one or more magnetic layers, a tunneling barrier layer underlying the first set of magnetic layers, and a second set of one or more magnetic layer underlying the tunneling barrier layer.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2010
From: SILICON MAGNETIC SYSTEMS
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 024651/0158 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2004
From: CHEN, EUGENE Y.; OUNADJELA, KAMEL; KULA, WITOLD; WOLFMAN, JEROME S.
To: SILICON MAGNETIC SYSTEMS
Reel/Frame 015025/0216 →