System and method for implementing a delta-sigma modulator integrity supervisor
View Patent ↗A system and a method for constructing a signal integrity supervisor capable of both detecting and triggering an appropriate response when transmit path signals indicate a potential damaging transmitter operating mode. The system and method of the present invention takes advantage of the inherent property of a Delta-Sigma Modulator (DSM) which makes the probability of encountering a long string of consecutive ones or zeroes during nominal operation very small. The signal integrity supervisor ensures safe transmitter operation by monitoring the data and the clock inputs to a digital to analog converter. The system may comprise a data signal supervisor and a clock signal supervisor. The data supervisor may comprise a comparator and a counter and may be configured to power down a line driver upon detecting a data stream having a continuous voltage level. The clock detector may comprise a pair of monostable circuits, an inverter, and a NAND gate and may be configured to reset the transmitter if a “missing” clock signal state is detected. The present invention can also be viewed as providing a method for preventing a transmission unit from forwarding signals that may result in a DC flow condition. In its broadest terms, the method can be described as: monitoring a data signal; generating a first output signal in response to a data signal having an anomalous condition; monitoring a clock signal; and generating a second output signal in response to clock signal having an anomalous condition.
1. A method for preventing a DC flow condition caused by a transmit signal, comprising:
monitoring a data signal to determine whether the data signal exhibits a change in value based on an asynchronous counter and a predetermined limit, wherein while monitoring the data signal, the asynchronous counter is updated or reset based on whether the data signal maintains a current logic level for multiple clock cycles;
generating a first signal in response to determining that the data signal does not exhibit a change in value to prevent the DC flow condition;
monitoring a clock signal; and
generating a second signal in response to a clock signal condition to prevent the DC flow condition.
2. The method of claim 1 , wherein the data signal is provided by a delta-sigma modulator.
3. The method of claim 1 , wherein the first signal is a power down signal.
4. The method of claim 3 , wherein the power down signal is generated by the asynchronous counter that reaches a maximum value.
5. The method of claim 1 , wherein the second signal is a reset signal.
6. The method of claim 5 , wherein the reset signal is generated in response to a clock signal having a frequency that fails to exceed a predetermined minimum value.
7. The method of claim 6 , wherein the reset signal is generated by a monostable circuit.
8. A method comprising:
monitoring a level of a data signal to determine whether a data signal condition exists, wherein monitoring a data signal comprises:
initializing an asynchronous counter;
updating the asynchronous counter when the level of the data signal is maintained for more than one clock cycle;
resetting the asynchronous counter when the level of the data signal is not maintained for more than one clock cycle; and
determining whether the asynchronous counter exceeds a predetermined limit;
generating a power down signal in response to the data signal condition to prevent a DC flow condition;
monitoring a clock signal; and
generating a reset signal in response to a clock signal condition to prevent the DC flow condition.
9. The method of claim 8 , wherein the data signal is provided by a delta-sigma modulator.
10. The method of claim 8 , wherein a clock signal condition exists if the clock signal has a frequency that fails to exceed a predetermined minimum value.
11. The method of claim 8 , wherein generating a reset signal comprises generating the reset signal using a monostable circuit.
12. A method comprising:
monitoring a level of a data signal, wherein monitoring comprises:
initializing an asynchronous counter;
updating the asynchronous counter when the level of the data signal is maintained for more than one clock cycle;
resetting the asynchronous counter when the level of the data signal is not maintained for more than one clock cycle; and
determining that a signal fault condition exists based on the asynchronous counter and a predetermined limit;
generating a power down signal if a signal fault condition exists;
monitoring for an anomalous clock signal comprising a clock signal with a frequency that fails to exceed a predetermined minimum value; and
generating a reset signal if an anomalous clock signal exists.
13. The method of claim 12 , wherein monitoring for an anomalous clock signal comprises monitoring how long the clock signal remains high and low.
14. The method of claim 13 , further comprising monitoring whether the clock signal remains high or low beyond a predetermined limit of time.
15. The method of claim 12 , wherein generating a reset signal comprises generating the reset signal using a monostable circuit.
16. The method of claim 12 , wherein monitoring a data signal comprises monitoring a data signal generated by a delta-sigma modulator.