Low dropout voltage regulator
View Patent ↗A low dropout voltage regulator (LDO) includes a regulating circuit, an amplifier, and a first compensating path. The regulating circuit is configured to receive an input signal at an input terminal and provide an output signal at an output terminal in response to a control signal received at the control terminal. The amplifier may have a first input terminal coupled to a first input path and an output terminal be coupled to the control terminal of the regulating circuit via a path to provide the control signal. The first compensating path is coupled between a first node on the first input path and a first node on the path coupling the output terminal of the amplifier to the control terminal of the regulating circuit, the first compensating path including a first compensating capacitor.
1. A low dropout voltage regulator (LDO) comprising:
a regulating circuit having an input terminal, an output terminal, and a control terminal, said regulating circuit configured to receive an input signal at said input terminal and provide an output signal at said output terminal in response to a control signal received at said control terminal;
an amplifier having a first and second input terminal and an output terminal, said first input terminal coupled to a first input path, said output terminal of said amplifier coupled to said control terminal of said regulating circuit via a path to provide said control signal;
a first compensating path coupled between a first node on said first input path and a first node on said path coupling said output terminal of said amplifier to said control terminal of said regulating circuit, said first compensating path comprising a first compensating capacitor; and
a second compensating path coupled between said output terminal of said regulating circuit and a second node on said path coupling said output terminal of said amplifier to said control terminal of said regulating circuit, said second compensating path comprising a second compensating capacitor.
2. The LDO of claim 1 , wherein said first input path comprises a resistor.
3. The LDO of claim 2 , wherein a feedback network is coupled between said output terminal of said regulating circuit and said second input terminal of said amplifier, wherein a second stage circuit comprises said regulating circuit and said feedback network, and wherein a first dominant pole is introduced in a frequency response plot of said LDO, said first dominant pone given by:
f
p1
=
1
2
π
[
R
S
(
1
+
A
)
C
1
+
r
01
(
1
+
B
)
C
2
]
where R S is a value of said resistor, A is a voltage gain of said amplifier, C 1 is a value of said first compensating capacitor, r O1 is an output impedance of said amplifier, B is a voltage gain of said second stage circuit, and C 2 is a value of said second compensating capacitor.
4. The LDO of claim 2 , wherein said first compensating capacitor and said resistor introduce a zero in a frequency response plot of said LDO, said zero given by:
f
z1
=
1
2
π
R
S
C
1
where R S is a value of said resistor and C 1 is a value of said first compensating capacitor.
5. The LDO of claim 1 , wherein said regulating circuit comprised a MOSFET transistor, said input terminal of said regulating circuit comprising a source terminal of said MOSFET transistor, said output terminal of said regulating circuit comprising a drain terminal of said MOSFET transistor, and said control terminal of said regulating circuit comprising a gate terminal of said MOSFET transistor.
6. An integrated circuit comprising:
a load; and
at least one low dropout voltage regulator (LDO) for providing a regulated output voltage to said load, said at least one LDO comprising:
a regulating circuit having an input terminal, an output terminal, and a control terminal, said regulating circuit configured to receive an input signal at said input terminal and provide an output signal at said output terminal in response to a control signal received at said control terminal;
an amplifier having a first and second input terminal and an output terminal, said first input terminal coupled to a first input path, said output terminal of said amplifier coupled to said control terminal of said regulating circuit via a path to provide said control signal;
a first compensating path coupled between a first node on said first input path and a first node on said path coupling said output terminal of said amplifier to said control terminal of said regulating circuit, said first compensating path comprising a first compensating; and
a second compensating path coupled between said output terminal of said regulating circuit and a second node on said path coupling said output terminal of said amplifier to said control terminal of said regulating circuit, said second compensating path comprising a second compensating capacitor.
7. The integrated circuit of claim 6 , wherein said first input path comprised a resistor.
8. The integrated circuit of claim 7 , wherein a feedback network is coupled between said output terminal of said regulating circuit and said second input terminal of said amplifier, wherein a second stage circuit comprises said regulating circuit and said feedback network, and wherein a first dominant pole is introduced in a frequency response plot of said LDO, said first dominant pole given by:
f
p1
=
1
2
π
[
R
S
(
1
+
A
)
C
1
+
r
01
(
1
+
B
)
C
2
]
where R S is a value of said resistor, A is a voltage gain of said amplifier, C 1 is a value of said first compensating capacitor, r O1 is an output impedance of said amplifier, B is a voltage gain of said second stage circuit, and C 2 is a value of said second compensating capacitor.
9. The integrated circuit of claim 7 , wherein said first compensating capacitor and said resistor introduce a zero in a frequency response plot of said LDO, said zero given by:
f
z1
=
1
2
π
R
S
C
1
where R S is a value of said resistor and C 1 is a value of saidfirst compensating capacitor.
10. An electronic device comprising:
an integrated circuit, said integrated circuit comprising at least one low dropout voltage regulator (LDO), for providing a regulated output voltage to a load of said integrated circuit, said at least one LDO comprising:
a regulating circuit having an input terminal, an output terminal, and a control terminal, said regulating circuit configured to receive an input signal at said input terminal and provide an output signal at said output terminal in response to a control signal received at said control terminal;
an amplifier having a first and second input terminal and an output terminal, said first input terminal coupled to a first input path, said output terminal of said amplifier coupled to said control terminal of said regulating circuit via a path to provide said control signal;
a first compensating path coupled between a first node on said first input path and a first node on said path coupling said output terminal of said amplifier to said control terminal of said regulating circuit, said first compensating path comprising a first compensating capacitor; and
a second compensating path coupled between said output terminal of said regulating circuit and a second node on said path coupling said output terminal of said amplifier to said control terminal of said regulating circuit, said second compensating path comprising a second compensating capacitor.
11. The electronic device of claim 10 , wherein said first input path comprises a resistor.
12. The electronic device of claim 11 , wherein a feedback network is coupled between said output terminal of said regulating circuit and said second input terminal of said amplifier, wherein a second stage circuit comprises said regulating circuit and said feedback network, and wherein a first dominant pole is introduced in a frequency response plot of said LDO, said first dominant pone given by:
f
p1
=
1
2
π
[
R
S
(
1
+
A
)
C
1
+
r
01
(
1
+
B
)
C
2
]
where R S is a value of said resistor, A is a voltage gain of said amplifier, C 1 is a value of said first compensating capacitor, r O1 is an output impedance of said amplifier, B is a voltage gain of said second stage circuit, and C 2 is a value of said second compensating capacitor.
13. The electronic device of claim 11 , wherein said first compensating capacitor and said resistor introduce a zero in a frequency response plot of said LDO, said zero given by:
f
z1
=
1
2
π
R
S
C
1
where R S is a value of said resistor and C 1 is a value of said first compensating capacitor.
14. A method of compensating a low dropout voltage (LDO) regulator comprising:
introducing a first dominant pole in a frequency response plot of said LDO;
introducing a second parasitic pole in said frequency response plot; and
introducing a first zero in said frequency response plot, said first zero resulting in a first phase shift that at least partially cancels with a second phase shift introduced by said second parasitic pole.
15. The method of claim 14 , wherein said second parasitic pole occurs at a first frequency level and said first zero occurs at a second frequency level, said second frequency level less than said first frequency level.