Integrated circuit with enhancement mode pseudomorphic high electron mobility transistors having on-chip electrostatic discharge protection
View Patent ↗An integrated circuit (IC) with high electron mobility transistors, such as enhancement mode pseudomorphic high electron mobility transistors (E-pHEMTs) and method for fabricating the IC utilizes an increased gate-to-drain etch recess spacing in some of the high electron mobility transistors to provide on-chip electrostatic discharge protection. The use of the increased gate-to-drain etch recess spacing allows smaller high electron mobility transistors to be used for ancillary low speed applications on the IC, which reduces the chip area occupied by these ancillary transistors.
1. An integrated circuit comprising:
a substrate; and
a high electron mobility transistor formed on the substrate, the high electron mobility transistor including a source electrode, a drain electrode and a gate electrode, the high electron mobility transistor having an increased gate-to-drain etch recess spacing, wherein the increased gate-to-drain etch recess spacing is at least four microns, the increased gate-to-drain etch recess spacing proving a greater protection for the high electron mobility transistor from an electrostatic discharge on the drain electrode.
2. The integrated circuit of claim 1 wherein the high electron mobility transistor includes an enhancement mode pseudomorphic high electron mobility transistor.
3. The integrated circuit of claim 1 further comprising a second high electron mobility transistor formed on the substrate on a signal path between an input node and an output node, the second high electron mobility transistor having a second gate-to-drain etch recess spacing, the gate-to-drain etch recess spacing of the high electron mobility transistor being wider than the second gate-to-drain etch recess spacing of the second high electron mobility transistor.
4. The integrated circuit of claim 3 wherein a width of the gate electrode of the high electron mobility transistor is wider than a width of a gate electrode of the second high electron mobility transistor.
5. The integrated circuit of claim 1 further comprising a resistor formed over the substrate connected to the drain electrode of the high electron mobility transistor, the resistor being made of a semiconductor material.
6. The integrated circuit of claim 1 further comprising a reverse biased Schottky diode formed over the substrate connected to the drain electrode of the high electron mobility transistor, the reverse biased Schottky diode being configured to have an increased anode-to-cathode etch recess spacing to provide protection for the reverse biased Schottky diode from a positive electrostatic discharge.
7. The integrated circuit of claim 6 wherein the reverse biased Schottky diode is structurally configured to turn on prior to the high electron mobility transistor when a negative electrostatic discharge is applied to the drain electrode of the high electron mobility transistor.
8. A method for fabricating an integrated circuit with at least one high electron mobility transistor, the method comprising:
proving a substrate; and
forming a high electron mobility transistor with a source electrode, a drain electrode and a gate electrode on the substrate, including creating an increased gate-to-drain etch recess spacing of at least four microns, the increased gate-to-drain etch recess spacing proving a greater protection for the high electron mobility transistor from an electrostatic discharge on the drain electrode.
9. The method of claim 8 wherein the forming of the high electron mobility transistor includes forming an enhancement mode pseudomorphic high electron mobility transistor on the substrate.
10. The method of claim 8 further comprising forming a second high electron mobility transistor on the substrate on a signal path between an input node and an output node, the second high electron mobility transistor having a second gate-to-drain etch recess spacing, the gate-to-drain etch recess spacing of the high electron mobility transistor being wider than the second gate-to-drain etch recess spacing of the second high electron mobility transistor.
11. The method of claim 10 wherein the forming the high electron mobility transistor includes creating the gate electrode with a width that is wider than a width of a gate electrode of the second high electron mobility transistor.
12. The method of claim 8 further comprising forming a resistor over the substrate connected to the drain electrode of the high electron mobility transistor, the resistor being made of a semiconductor material.
13. The method of claim 8 further comprising forming a reverse biased Schottky diode over the substrate connected to the drain electrode of the high electron mobility transistor, including creating an increased anode-to-cathode etch recess spacing to provide protection for the reverse biased Schottky diode from a positive electrostatic discharge.
14. An integrated circuit comprising:
an insulating substrate;
a first high electron mobility transistor formed on the insulating substrate, the first high electron mobility transistor having a first gate-to-drain etch recess spacing; and
a second high electron mobility transistor formed on the insulating substrate, the second high electron mobility transistor having a second gate-to-drain etch recess spacing that is wider than the first gate-to-drain etch recess spacing of the first high electron mobility transistor to provide a greater protection for the second high electron mobility transistor from an electrostatic discharge.
15. The integrated circuit of claim 14 wherein the second gate-to-drain etch recess spacing of the second high electron mobility transistor is at least four microns.
16. The integrated circuit of claim 14 wherein a width of a gate electrode of the second high electron mobility transistor is wider than a width of a gate electrode of the first high electron mobility transistor.
17. The integrated circuit of claim 14 further comprising a resistor formed over the substrate connected to a drain electrode of the second high electron mobility transistor, the resistor being made of a semiconductor material.
18. The integrated circuit of claim 14 further comprising a reverse biased Schottky diode formed over the insulating substrate connected to the second high electron mobility transistor, the reverse biased Schottky diode being configured to have an anode-to-cathode etch recess spacing that is wider than the first gate-to-drain etch recess spacing of the first high electron mobility transistor to provide protection for the reverse biased Schottky diode from the positive electrostatic discharge.
19. A method for fabricating an integrated circuit with at least one high electron mobility transistor, the method comprising:
proving a substrate;
forming a high electron mobility transistor with a source electrode, a drain electrode and a gate electrode on the substrate, including creating an increased gate-to-drain etch recess spacing, the increased gate-to-drain etch recess spacing proving a greater protection for the high electron mobility transistor from an electrostatic discharge on the drain electrode; and
forming a second high electron mobility transistor on the substrate on a signal path between an input node and an output node, the second high electron mobility transistor having a second gate-to-drain etch recess spacing, the gate-to-drain etch recess spacing of the high electron mobility transistor being wider than the second gate-to-drain etch recess spacing of the second high electron mobility transistor.
20. The method of claim 19 wherein the forming the high electron mobility transistor includes creating the gate electrode with a width that is wider than a width of a gate electrode of the second high electron mobility transistor.