IP Library Granted Patent US 7,045,420
Granted Patent B2
US 7,045,420 · App. 10/793,840 · Granted May 16, 2006

Semiconductor device comprising capacitor and method of fabricating the same

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Quick Facts
Patent No.
US 7,045,420
App. No.
10/793,840
Granted
May 16, 2006
Kind
B2
Abstract

A high density semiconductor device is formed with a constant capacitor capacitance. The semiconductor device includes a memory cell region and a peripheral circuit region. An insulating film, having an upper surface, is formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. The upper surface of the insulating film is located between the top surface and the bottom surface of the capacitor lower electrode part.

Claims (20)

1. A method of fabricating a semiconductor device including a memory cell region and a peripheral circuit region, comprising steps of:

forming an insulating film having an upper surface on a major surface of a semiconductor substrate to extend from said memory cell region to said peripheral circuit region;

partially removing said insulating film by etching in said memory cell region thereby forming an opening;

forming a capacitor lower electrode in said opening on said major surface of said semiconductor substrate; and

forming a capacitor upper electrode on said capacitor lower electrode through a dielectric film to extend onto said upper surface of said insulating film, wherein

said step of forming said capacitor lower electrode includes a step of forming a capacitor lower electrode part upwardly extending in opposition to said capacitor upper electrode and having a top surface and a bottom surface,

said step of forming said insulating film includes a step of locating said upper surface of said insulating film between said top surface and said bottom surface of said capacitor lower electrode part,

said step of forming said insulating film includes steps of:

forming a lower insulating film, and

forming an upper insulating film being different in etching rate from said lower insulating film on said lower insulating film, and

said step of locating said upper surface of said insulating film between said top surface and said bottom surface of said capacitor lower electrode part includes a step of removing said upper insulating film.

2. The method of fabricating a semiconductor device in accordance with claim 1 , wherein

said step of locating said upper surface of said insulating film between said top surface and said bottom surface of said capacitor lower electrode part includes a step of partially removing said insulating film by etching.

3. The method of fabricating a semiconductor device in accordance with claim 1 , further comprising steps of:

forming a conductive region on said major surface of said semiconductor substrate in a region located under said capacitor lower electrode,

forming an interlayer isolation film on said conductive region,

forming a wiring layer on said interlayer isolation film,

forming a wire protection film on said wiring layer, and

removing a part of at least said interlayer insulating film by etching thereby forming a contact hole for electrically connecting said conductive region with said capacitor lower electrode,

said wire protection film being employed as a part of a mask employed for etching in said step of forming said contact hole.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 057454/0045 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 052853 FRAME 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Mar 2, 2021
From: ACACIA RESEARCH GROUP LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056775/0066 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
CHANGE OF NAME Recorded Sep 10, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024973/0001 →