Nonvolatile memory solution using single-poly pFlash technology
View Patent ↗A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.
1. A single-poly two-transistor (2T) PMOS memory cell, comprising:
a PMOS soled gate transistor having a drain and a source formed as separate p+ diffusion regions in a first n-well;
a PMOS floating gate transistor having a drain and a source formed as separate P+ diffusion regions in the n-well, wherein the p+ diffusion region that forms the floating gate transistor's drain is the same p+ diffusion region that forms the select gate transistor's source; and
a control plate for the PMOS floating gate transistor formed within a second n-well well, the second n-well being separated from the first n-well.
2. The 2T PMOS memory cell of claim 1 , wherein an extension of a floating gate for the PMOS floating gate transistor overlays the separate n-well, the control plate being formed by that portion of the second n-well covered by the extension of the floating gate.
3. The 2T PMOS memory cell of claim 2 , wherein the extension of the floating gate is doped n+ and the second n-well has an n-type type threshold adjust implant.
4. The 2T PMOS memory cell of claim 3 , wherein the n-type doping of the extension of the floating gate and threshold adjust implant is such that their Fermi levels are substantially equal.
5. The 2T PMOS memory cell of claim 2 , wherein the extension of a floating gate for overlaying the second n-well includes a digitated portion comprising finger extensions.
6. The 2T PMOS memory cell of claim 5 , wherein the second n-well includes LDD implants between adjacent fingers of the digitated portion.
7. The 2T PMOS memory cell of claim 6 , wherein the finger extensions are bounded by LDD spacers, the second n-well including an n+ diffusion region between adjacent finger extension's LDD spacers.