Low voltage high density trench-gated power device with uniformity doped channel and its edge termination technique
View Patent ↗Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N + substrate can be terminated at the edge of the die.
1. A method for manufacturing a power mosfet comprising the steps of:
forming a gate trench mask with open and closed regions on the surface of a semiconductor substrate;
removing semiconductor material from areas exposed by the open regions of the trench mask to form a plurality of gate trenches;
forming a sacrificial gate oxide layer on the sidewalls of the trenches;
implanting the substrate with a drift region implant that penetrates the oxide on the floors of the trenches and is stopped on the surface of the substrate by the residual trench mask;
annealing the substrate to diffuse the drift implant to form a continuous drift layer and define the length of the gate;
removing the trench mask and the sacrificial oxide and forming a gate oxide on the surface of the trench;
depositing a layer of polysilicon on the surface of the substrate and in the trenches;
removing the polysilicon from the surface of the semiconductor substrate and leaving enough polysilicon in the gate trenches to form gates in the trenches;
implanting the substrate with a source dopant to form source regions in the surface of the semiconductor substrate and to increase the conductivity of the polysilicon in the trenches to form gate regions in the trenches;
depositing a layer of BPSG on the substrate;
removing at least apart of the BPSG layer to expose portions of the surface having the source implant;
depositing and patterning a conductive layer over the surface of the substrate to form electrical contacts to the source regions.
2. The method of claim 1 further comprising the steps of:
etching a step having a vertical face and a horizontal ledge on the edge of the die while etching the trenches;
forming a gate runner on an upper surface proximate the vertical face;
forming a heavily doped channel stop region in the horizontal ledge at the edged of the die with dopants of the same polarity as the source region; and
forming a metal contact layer over and in contact with the channel stop region.