Semiconductor device and manufacturing method thereof
View Patent ↗A plurality of semiconductor chips ( 14 ) each having a first main surface ( 14 b ) formed with electrode pads ( 21 ) and a second main surface ( 14 c ) opposite to the first main surface are respectively mounted on a chip mounting surface ( 12 a ) larger in area than the second main surface, of a wafer-shaped mounting substrate ( 12 ) at equal intervals so as to extend along first and second trenches ( 18 a, 18 b ) defined in the chip mounting surface with these trenches as target lines. Thereafter, solder balls ( 25 ) electrically connected to the electrode pads of the semiconductor chips are disposed on their corresponding wiring patterns 34 that extend from above first regions ( 100 ) located above the semiconductor chips, of a surface region of an encapsulating layer ( 32 ) covering the semiconductor chips to above second regions ( 200 ) that surround the first regions. Afterwards, the encapsulating layer and the mounting substrate are cut and thereby fractionized into semiconductor devices each having a fan-out structure.
1. A semiconductor device comprising:
a semiconductor chip having a first main surface formed with electrode pads and a second main surface opposite to the first main surface;
a mounting substrate having a chip mounting surface which has an area wider than an area of the second main surface and is opposed in face to face contact with the second main surface, the semiconductor chip being mounted on said mounting substrate;
an encapsulating layer formed on the chip mounting surface so as to cover the semiconductor chip;
wiring patterns electrically connected to the electrode pads and extending in contact with the encapsulating layer from a first region to a second region, the first region being located on the surface of the encapsulating layer which is located above the semiconductor chip and the second region being located on the surface of the encapsulating layer which surrounds the first region;
external terminals disposed on the surfaces of the wiring patterns located on the second region, and
a first trench formed on the mounting surface and extending from a first side surface of the mounting substrate to a second side surface of the mounting substrate opposite to the first side surface of the mounting substrate, wherein the encapsulating layer is formed in the first trench.
2. A semiconductor device according to claim 1 , wherein the semiconductor chip is mounted on the mounting substrate along the first trench.
3. A semiconductor device according to claim 1 , wherein the semiconductor chip is mounted on the mounting substrate in alignment with the first trench.
4. A semiconductor device according to claim 1 , wherein the semiconductor chip is mounted on the mounting substrate with being spaced a predetermined distance from the first trench.
5. A semiconductor device according to claim 1 , wherein the side surfaces of the mounting substrate and the encapsulating layer are cut sections.
6. A semiconductor device according to claim 1 , further comprising a second trench formed on the mounting surface and extending from a third side surface of the mounting substrate to a fourth side surface opposite to the third side surface of the mounting substrate.
7. A semiconductor device according to claim 6 , wherein the corner of the semiconductor chip is mounted in alignment with the corner of the chip mounting surface, which is formed by causing the first and second trenches to intersect.
8. A semiconductor device according to claim 6 , wherein the semiconductor chip is mounted with being shifted in parallel with respect to the first and second trenches respectively.
9. A semiconductor device comprising:
a semiconductor chip having a first main surface formed with electrode pads and a second main surface opposite to the first main surface;
a mounting substrate having a chip mounting surface which has an area wider than an area of the second main surface and is opposed face to face with the second main surface, the semiconductor chip being mounted on said mounting substrate;
an encapsulating layer formed on the chip mounting surface so as to cover the semiconductor chip;
wiring patterns electrically connected to the electrode pads and extending in contact with the encapsulating layer from a first region to a second region, the first region being located on the surface of the encapsulating layer which is located above the semiconductor chip and the second region being located on the surface of the encapsulating layer which surrounds the first region;
external terminals disposed on the surfaces of the wiring patterns located on the second region; and
a protruding portion formed on the mounting surface and extending from a first side surface of the mounting substrate to a second side surface of the mounting substrate opposite to the first side surface of the mounting substrate, wherein the protruding portion is covered with the encapsulating layer.
10. A semiconductor device according to claim 1 , wherein the external terminals comprise solder balls.
11. A semiconductor device according to claim 9 , wherein the external terminals comprise solder balls.
12. A semiconductor device according to claim 1 , wherein the second region is located on the surface of the encapsulating layer above a portion of the mounting substrate outside of the semiconductor chip.
13. A semiconductor device according to claim 9 , wherein the second region is located on the surface of the encapsulating layer above a portion of the mounting substrate outside of the semiconductor chip.