IP Library Granted Patent US 6,891,407
Granted Patent B2
US 6,891,407 · App. 10/799,668 · Granted May 10, 2005

Analog signal level detecting apparatus

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Quick Facts
Patent No.
US 6,891,407
App. No.
10/799,668
Granted
May 10, 2005
Kind
B2
Abstract

A rectified analog input signal is compared with a threshold voltage by a voltage comparator, and counting direction of an up/down counter is switched based on the comparison result, and a latch circuit retains an output of the up/down counter, and then an analog-digital converting circuit converts an output of the latch signal into a direct-current voltage. In addition, two input terminals, to which a clock for up-count operation and a clock for down-count operation are independently provided, is provided in the up/down counter, and a timing pulse generating circuit for determining reset timing of the up/down counting circuit and latch timing of the latch circuit is provided.

Claims (10)

1. An analog signal level detecting apparatus comprising:

a first voltage comparator for comparing an input signal with a reference voltage;

a rectifying circuit for rectifying said input signal;

a second voltage comparator for comparing an output signal of said rectifying circuit with a threshold voltage specified previously arbitrarily;

an up/down counting circuit, to which a clock for an up-count operation and a clock for a down-count operation are independently provided, for selectively performing an up-count operation or a down-count operation according to an output signal of said second voltage comparator;

a first latch circuit for retaining a count value of said up/down counting circuit;

a timing pulse generating circuit for generating a timing pulse, which determines reset timing of said up/down counting circuit and retaining timing of said first latch circuit, based on an output signal of said first voltage comparator;

a digital-analog converting circuit for converting an output signal of said first latch circuit into a direct-current voltage.

2. The analog signal level detecting apparatus according to claim 1 further comprising a wave-shaping circuit, which is provided between said second voltage comparator and said up/down counting circuit, for stopping conveying a change of the output signal of the second voltage comparator in time of a period of a clock with a shorter period of said clock for an up-count operation and said clock for a down-count operation to said up/down counting circuit.

3. The analog signal level detecting apparatus according to claim 2 , wherein said wave-shaping circuit includes a second latch circuit for performing an updating operation at the period of a clock with a shorter period of said clock for an up-count operation and said clock for a down-count operation.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2014
From: PANASONIC CORPORATION
To: COLLABO INNOVATIONS, INC.
Reel/Frame 033021/0806 →
LIEN Recorded Jan 13, 2014
From: COLLABO INNOVATIONS, INC.
To: PANASONIC CORPORATION
Reel/Frame 031997/0445 →
CHANGE OF NAME Recorded Jan 8, 2014
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 031947/0358 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2004
From: KOBAYASHI, TAKU; FUJII, KEIICHI; ISHIDA, TAKUMA
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 015092/0028 →