IP Library Granted Patent US 6,941,077
Granted Patent B2
US 6,941,077 · App. 10/800,177 · Granted Sep 6, 2005

Memory mapped monitoring circuitry for optoelectronic device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,941,077
App. No.
10/800,177
Granted
Sep 6, 2005
Kind
B2
Abstract

Circuitry for monitoring operation of an optoelectronic device having a laser transmitter and a photodiode receiver includes analog to digital conversion circuitry for receiving a plurality of analog signals from the laser transmitter and photodiode receiver, converting the received analog signals into digital values, and storing the digital values in predefined memory-mapped locations within the optoelectronic device. Comparison logic compares one or more of these digital values with limit values, generates flag values based on the comparisons, and stores the flag values in predefined locations within the optoelectronic device. An interface enables a host device to read from and write to host-specified memory mapped locations within the optoelectronic device.

Claims (36)

1. Circuitry for monitoring an optoelectronic device, comprising:

memory, including one or more memory arrays for storing information related to the optoelectronic device;

analog to digital conversion circuitry configured to receive a plurality of analog signals from the optoelectronic device, the analog signals corresponding to operating conditions of the optoelectronic device, convert the received analog signals into digital values, and store the digital values in predefined locations within the memory;

comparison logic configured to compare the digital values with limit values to generate flag values, wherein the flag values are stored in predefined flag storage locations within the memory during operation of the optoelectronic device; and

an interface configured to enable a host to read directly from and write directly to locations within the memory, including the predefined flag storage locations, in accordance with commands received from the host.

2. The circuitry of claim 1 , wherein the analog to digital conversion circuitry is configured to convert a power level signal into a digital power level value and to store the digital power level value in a predefined power level location within the memory.

3. The circuitry of claim 2 , wherein the comparison logic includes logic for comparing the digital power level value with a power limit value, generating a power flag value based on the comparison of the digital power signal with the power limit value, and storing the power flag value in a predefined power flag location within the memory.

4. The circuitry of claim 1 , wherein the analog to digital conversion circuitry is configured to convert a temperature signal into a digital temperature value and to store the digital temperature value in a predefined temperature location within the memory.

5. The circuitry of claim 4 , wherein the comparison logic includes logic for comparing the digital temperature value with a temperature limit value, generating a temperature flag value based on the comparison of the digital temperature signal with the temperature limit value, and storing the temperature flag value in a predefined temperature flag location within the memory.

6. The circuitry of claim 1 , wherein the plurality of analog signals includes two analog signals selected from the set consisting of laser bias current, laser output power, and received power.

7. The circuitry of claim 1 , wherein the analog to digital conversion circuitry is configured to receive a voltage signal from a source external to the monitoring circuitry, convert the voltage signal into a digital voltage value and store the digital voltage value in a respective predefined location within the memory.

8. Circuitry for monitoring an optoelectronic device, comprising:

memory, including one or more memory arrays for storing information related to the optoelectronic device;

analog to digital conversion circuitry configured to receive a plurality of analog signals from the optoelectronic device, the analog signals corresponding to operating conditions of the optoelectronic device, convert the received analog signals into digital values, and store the digital values in predefined locations within the memory;

comparison logic configured to compare the digital values with limit values to generate flag values, wherein the flag values are stored in predefined flag storage locations within the memory during operation of the optoelectronic device; and

an interface configured to enable a host to read directly from and write directly to locations within the memory, including the predefined flag storage locations, in accordance with commands received from the host;

wherein the plurality of analog signals include laser bias current, laser output power, and received power.

9. A method of monitoring an optoelectronic device, comprising:

receiving a plurality of analog signals from the optoelectronic device, the analog signals corresponding to operating conditions of the optoelectronic device, converting the received analog signals into digital values, and storing the digital values in predefined locations within a memory;

comparing the digital values with limit values to generate flag values, and storing the flag values in predefined flag locations within the memory; and

in accordance with instructions received from a host device, enabling the host device to read directly from and write directly to locations within the memory, including the predefined flag locations.

10. The method of claim 9 , further including:

generating a power level signal corresponding to a power supply voltage level of the optoelectronic device, converting the power level signal into a digital power level value and storing the digital power level value in a predefined power level location within the memory.

11. The method of claim 10 , further including:

comparing the digital power level value with a power level limit value, generating a power level flag value based on the comparison of the digital power level signal with the power level limit value, and storing the power level flag value in a predefined power level flag location within the memory.

12. The method of claim 9 , further including

generating a temperature signal corresponding to a temperature of the optoelectronic device, converting the temperature signal into a digital temperature value and storing the digital temperature value in a predefined temperature location within the memory.

13. The method of claim 12 , wherein

comparing the digital temperature value with a temperature limit value, generating a temperature flag value based on the comparison of the digital temperature signal with the temperature limit value, and storing the temperature flag value in a predefined temperature flag location within the memory.

14. The method of claim 9 , wherein the plurality of analog signals includes two analog signals selected from the set consisting of laser bias current, laser output power, and received power.

15. The method of claim 9 , including receiving a voltage signal from a source external to the optoelectronic device, converting the voltage signal into a digital voltage value and storing the digital voltage value in a respective predefined location within the memory.

16. A method of monitoring an optoelectronic device, comprising:

receiving a plurality of analog signals from the optoelectronic device, the analog signals corresponding to operating conditions of the optoelectronic device, converting the received analog signals into digital values, and storing the digital values in predefined locations within a memory;

comparing the digital values with limit values to generate flag values, and storing the flag values in predefined flag locations within the memory; and

in accordance with instructions received from a host device, enabling the host device to read directly from and write directly to locations within the memory, including the predefined flag locations;

wherein the plurality of analog signals includes laser bias current, laser output power, and received power.

Assignments (6)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2019
From: ARONSON, LEWIS B.; HOSKING, STEPHEN G.
To: FINISAR CORPORATION
Reel/Frame 049253/0221 →
RELEASE OF SECURITY INTEREST Recorded Oct 6, 2016
From: WELLS FARGO CAPITAL FINANCE, LLC
To: FINISAR CORPORATION; OPTIUM CORPORATION; AZNA LLC; FINISAR SALES, INC.; KAILIGHT PHOTONICS, INC.
Reel/Frame 040248/0860 →
SECURITY AGREEMENT Recorded Nov 10, 2009
From: FINISAR CORPORATION; OPTIUM CORPORATION; AZNA LLC; FINISAR SALES, INC.; KAILIGHT PHOTONICS, INC.
To: WELLS FARGO FOOTHILL, LLC, AS AGENT
Reel/Frame 023486/0741 →