Semiconductor integrated circuit device having diagonal direction wiring and layout method therefor
View Patent ↗A semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, includes an orthogonal wire having a first minimum wire width which is formed on a first wiring layer and extends horizontally or vertically; a diagonal wire having a second minimum wire width which is substantially equal to the first minimum wire width, formed on a second wiring layer which differs from the first wiring layer and extending in a diagonal direction in relation to the orthogonal wire; and a via having a size which is no greater than the first or second wire width, formed at point at which the orthogonal wire and diagonal wire overlap so as to connect the orthogonal wire and diagonal wire, wherein one of the diagonal wire and orthogonal wire includes an enlarged wire width region in the position at which the via is formed, the wire width of the enlarged wire width region being enlarged beyond the first or second minimum wire width.
1. A semiconductor integrated circuit device having a plurality of circuit elements and a plurality of wires connecting the circuit elements, comprising:
an orthogonal wire having a first minimum wire width, which is formed in a first wiring layer and extends horizontally or vertically;
a diagonal wire having a second minimum wire width which is substantially equal to said first minimum wire width, which is formed in a second wiring layer which differs from said first wiring layer and extending in a diagonal direction in relation to said orthogonal wire; and
a via having a size which is no greater than said first or second minimum wire width, which is formed at point at which said orthogonal wire and said diagonal wire overlap so as to connect said orthogonal wire and said diagonal wire,
wherein one of said diagonal wire and said orthogonal wire includes an enlarged wire width region in a position at which said via is formed, the wire width of said enlarged wire width region being enlarged beyond said first or second minimum wire width.
2. The semiconductor integrated circuit according to claim 1 , wherein said via has a rectangular form in which the length of one edge is shorter than said first or second minimum wire width, the rectangle is provoded in the same direction as one of said diagonal wire and said orthogonal wire, and the other of said diagonal wire and said orthogonal wire includes said enlarged wire width region.