Wiring, display device and method of manufacturing the same
View Patent ↗The present invention provides a wiring, a display device, and a method of manufacturing the same. A first metal diffusion-preventing layer is formed on a substrate or on a circuit element formed on the substrate. Then, a metal wiring layer is selectively formed on the first metal diffusion-preventing layer by an electroless metal plating method or a metal electroplating method. Further, the undesired portion of the first metal diffusion-preventing layer is removed. Finally, a second metal diffusion-preventing layer is formed selectively by an electroless metal plating method in a manner to cover the metal wiring layer or both a seed layer and the metal wiring layer.
1. A thin-film transistor comprising:
an island-shaped silicon layer which is provided on an insulating substrate;
a source region and a drain region which are provided with an interval on the silicon layer on the insulating substrate;
a gate insulator layer which is provided over the silicon layer between the source region and the drain region;
a gate electrode which is provided on the gate insulator layer; and
a source electrode and a drain electrode which are provided on the source region and the drain region, respectively, wherein
the gate electrode comprises:
a first copper diffusion-preventing layer formed by an electroless metal plating method on the gate insulator layer;
a copper seed layer in which an undesired portion is removed on the first copper diffusion-preventing layer;
a copper layer formed on the copper seed layer of which the undesired portion is removed, the copper layer being formed by the electroless metal plating method and a film thickness of the copper layer being greater than that of the copper seed layer; and
a second copper diffusion-preventing layer surrounding an exposed surface including side upper surfaces of a multilayered structure having the copper seed layer and the copper layer, the second copper diffusion-preventing layer being formed by the electroless metal plating method, and wherein
the copper seed layer and the copper layer are surrounded by the first copper diffusion-preventing layer and the second copper diffusion-preventing layer, and have a forward tapered cross section.
2. The thin-film transistor according to claim 1 , wherein the source electrode and the drain electrode comprises:
a third copper diffusion-preventing layer formed on the source region and the drain region;
a copper wiring layer formed on the third copper diffusion-preventing layer; and
a fourth copper diffusion-preventing layer formed to surround the copper wiring layer.
3. The thin-film transistor according to claim 2 , wherein a plurality of the thin-film transistors are arranged to form a matrix, and the thin-film transistors have scanning lines connected to the gate electrodes of the thin-film transistors, and signal lines connected to one of the source electrodes and the drain electrodes of the thin-film transistors, the signal lines being provided such that they are surrounded by the first copper diffusion-preventing layer and the second copper diffusion-preventing layer.
4. The thin-film transistor according to claim 1 , wherein the insulating substrate is formed of one of glass, a quartz glass, ceramics, and a resin material.
5. A thin-film transistor comprising:
a silicon layer which is provided on an insulating substrate;
a source region and a drain region which are provided with an interval on the silicon layer on the insulating substrate:
a gate insulator layer which is provided on the silicon layer between the source region and the drain region;
a gate electrode which is provided on the gate insulator layer; and
a source electrode and a drain electrode which are provided on the source region and the drain region, respectively, wherein
the source electrode and the drain electrode comprise:
a first copper diffusion-preventing layer formed on the source region and the drain region;
an organometallic compound material layer having a forward tapered cross section formed on the first copper diffusion-preventing layer by removing an undesired portion;
a copper layer having a forward tapered cross section formed on the organometallic compound material layer of which the undesired portion is removed; and
a second copper diffusion-preventing layer covering an exposed surface including side and upper surfaces of a multilayered structure having the first copper diffusion-preventing layer, the copper layer and the organometallic compound material layer, and wherein
the organometallic compound material layer and the copper layer have a forward tapered cross section and are surrounded by the first copper diffusion-preventing layer and the second copper diffusion-preventing layer.
6. The thin-film transistor according to claim 5 , wherein the insulating substrate is formed of one of glass, a quartz glass, ceramics, and a resin material.
7. A thin-film transistor comprising:
an island-shaped silicon layer which is provided on an insulating substrate;
a source region and a drain region which are provided with an interval on the silicon layer on the insulating substrate;
a gate insulator layer which is provided on the silicon layer between the source region and the drain region;
a gate electrode which is provided on the gate insulator layer; and
a source electrode and a drain electrode which are provided on the source region and the drain region, respectively, wherein
the gate electrode comprises:
a first copper diffusion-preventing layer formed on the gate insulator layer;
a copper seed layer formed on the first copper diffusion-preventing layer;
a copper layer formed on the copper seed layer by an electroless metal plating method, a film thickness of the copper layer being greater than that of the copper seed layer; and
a second copper diffusion-preventing layer covering an exposed surface including side and upper surfaces of a multilayered structure having the first copper diffusion-preventing layer, the copper layer, and the copper seed layer, and wherein
the copper layer has a forward tapered cross section.
8. The thin-film transistor according to claim 7 , wherein the insulating substrate is formed of one of glass, a quartz glass, ceramics, and a resin material.
9. A thin-film transistor comprising:
a silicon layer which is provided on an insulating substrate;
a source region and a drain region which are provided with an interval on the silicon layer on the insulating substrate;
a gate insulator layer which is provided on the silicon layer between the source region and the drain region;
a gate electrode which is provided on the gate insulator layer; and
a source electrode and a drain electrode which are provided on the source region and the drain region, respectively, wherein
the source electrode and the drain electrode comprise:
a first copper diffusion-preventing layer formed on the source region and the drain region;
a nickel seed layer or a seed layer made of a metal material of group VIIIa including a cobalt seed layer which is formed on the first copper diffusion-preventing layer and of which an undesired portion is removed, the undesired portion being a portion other than an area where the source region and the drain region are formed;
a copper layer formed on the nickel seed layer or a seed layer made of a metal material of group VIIIa including a cobalt seed layer; and
a second copper diffusion-preventing layer covering an exposed surface including side; upper and lower surfaces of a multilayered structure having the nickel seed layer or a seed layer made of a metal material of group VIIIa including a cobalt seed layer and the copper layer, and wherein
the nickel seed layer or a seed layer made of a metal material of group VIIIa including a cobalt seed layer and the copper layer are surrounded by the first copper diffusion-preventing layer and the second copper diffusion-preventing layer, and have a forward tapered cross section.