System and method to reduce noise in a substrate
View Patent ↗Certain embodiments of the invention may be found in, for example, a system that reduces noise in a substrate of a chip and may comprise a substrate layer that is integrated within the chip. A transistor layer is integrated within the chip and is shielded from the substrate layer by a shielding layer. At least one transistor of a first transistor type couples the transistor layer to the shielding layer and a quiet voltage source may be coupled to the transistor of the first transistor type. At least one transistor of a second transistor type is coupled to the shielding layer. The transistor of the second transistor type may be a n-type transistor, which may be disposed within the transistor layer and the transistor of the second transistor type may be resistively coupled to the shielding layer.
1. A system for reducing noise in a chip, the system comprising:
a substrate layer integrated within the chip;
a transistor layer integrated within the chip, which is shielded from said substrate layer by a shielding layer, wherein said shielding layer reduces transfer of noise in the chip;
at least one transistor of a first transistor type that couples said transistor layer to said shielding layer;
a positive potential of a quiet voltage source that is coupled to said at least one transistor of said first transistor type; and
a noisy voltage source coupled to said at least one transistor of a first transistor type.
2. The system according to claim 1 , wherein said noisy voltage source is coupled to a source of said at least one transistor of a first transistor type.