Method and system for providing transport of channelized circuits of arbitrary bit rate through asynchronous transfer mode (ATM) circuit emulation services (CES)
View Patent ↗A system for managing circuit emulation service over an Asynchronous Transfer Mode (ATM) network is provided. The system includes control logic configured to receive channelized circuit data from a client, the channelized circuit data being transmitted at an arbitrary rate. The channelized circuit data is formatted into one or more ATM cells. Each ATM cell has a payload. The payload has a number of octets and corresponding validity fields. Each validity field is used to indicate whether the associated octet contains valid data. The one or more ATM cells are transmitted across the ATM network. By examining the validity fields, the transmission of the one or more ATM cells effectively results in transmission of the channelized circuit data at the arbitrary rate over the ATM network. The arbitrary rate is not a multiple of a fundamental rate.
1. A system for managing circuit emulation service over an Asynchronous Transfer Mode (ATM) network, comprising:
control logic configured to receive channelized circuit data, the channelized circuit data being transmitted at an arbitrary rate;
control logic configured to format the channelized circuit data into one or more ATM cells, each ATM cell having a payload, the payload having a plurality of octets and corresponding validity fields, each validity field being associated with one octet of the plurality of octets, the validity field indicating whether the associated octet contains valid data, wherein the control logic is configured to selectively include data in a first subset of the plurality of octets and not include data in a second subset of the plurality of octets of each ATM cell of the one or more ATM cells so that transmission of the one or more ATM cells results in transmission of the channelized circuit data at the arbitrary rate, wherein the control logic is configured to set the validity fields associated with the first subset of the octets of the payload of each of the one or more ATM cells to a valid status to indicate that data is included in the first subset of octets, and wherein the control logic is further configured to set the validity fields associated with the second subset of the octets of the payload of each of the one or more ATM cells to an invalid status to indicate that no data is included in the second subset of octets; and
control logic configured to transmit the one or more ATM cells across the ATM network;
wherein the transmission of the one or more ATM cells effectively results in transmission of the channelized circuit data at the arbitrary rate over the ATM network;
wherein the arbitrary rate is achieved by adjusting a ratio of a number of octets in the first subset of octets to a number of octets in the second subset of octets for each of the one or more ATM cells; and
wherein the arbitrary rate is not a multiple of a fundamental rate.
2. The system of claim 1 wherein the arbitrary rate is less than the fundamental rate.
3. The system of claim 1 wherein the arbitrary rate is higher than the fundamental rate.
4. Traffic aggregation equipment incorporating the system as recited in claim 1 .
5. A system for managing circuit emulation service over an Asynchronous Transfer Mode (ATM) network, comprising:
a first ATM processor configured to:
receive channelized circuit data, the channelized circuit data being transmitted at an arbitrary rate;
format the channelized circuit data into one or more ATM cells, each ATM cell having a payload, the payload having a plurality of octets and corresponding validity fields, each validity field being associated with one octet of the plurality of octets, the validity field indicating whether the associated octet contains valid data, wherein the first ATM processor is configured to selectively include data in a first subset of the plurality of octets and not include data in a second subset of the plurality of octets of each ATM cell of the one or more ATM cells so that transmission of the one or more ATM cells results in transmission of the channelized circuit data at the arbitrary rate, wherein the first ATM processor is configured to set the validity fields associated with the first subset of the octets of the payload of each of the one or more ATM cells to a valid status to indicate that data is contained in the first subset of octets, and wherein the first AMT processor is further configured to set the validity fields associated with the second subset of the octets of the payload of each of the one or more ATM cells to an invalid status to indicate that no data is contained in the second subset of octets; and
transmit the one or more ATM cells across the ATM network; and
a second ATM processor configured to receive and process the one or more ATM cells transmitted from the first ATM processor;
wherein the transmission of the one or more ATM cells effectively results in transmission of the channelized circuit data at the arbitrary rate over the ATM network;
wherein the arbitrary rate is achieved by adjusting a ratio of a number of octets in the first subset of octets to a number of octets in the second subset of octets for each of the one or more ATM cells; and
wherein the arbitrary rate is not a multiple of a fundamental rate.
6. The system of claim 5 wherein the second ATM processor processes each ATM cell based on the validity fields and the associated octets contained therein;
wherein if a validity field indicates a “valid” status, the associated octet is considered to be containing valid data and will be processed, and if the validity field indicates an “invalid” status, the associated octet is considered to be containing invalid data and will not be processed; and
wherein by processing the one or more ATM cells based on the validity fields contained therein, the transmission of the one or more ATM cells effectively results in transmission of the channelized circuit data at the arbitrary rate over the ATM network.
7. The system of claim 5 wherein the arbitrary rate is less than the fundamental rate.
8. The system of claim 5 wherein the arbitrary rate is higher than the fundamental rate.
9. A method for managing circuit emulation service over an Asynchronous Transfer Mode (ATM) network, the method comprising:
receiving channelized circuit data, the channelized circuit data being transmitted at an arbitrary rate;
formatting the channelized circuit data into one or more ATM cells, each ATM cell having a payload, the payload having a plurality of octets and corresponding validity fields, each validity field being associated with one octet of the plurality of octets, the validity field indicating whether the associated octet contains valid data, wherein formatting the channelized circuit data into one or more ATM cells further comprises:
selectively including data in a first subset of the plurality of octets and not include data in a second subset of the plurality of octets of each ATM cell of the one or more ATM cells so that transmission of the one or more ATM cells results in transmission of the channelized circuit data at the arbitrary rate;
setting the validity fields associated with the first subset of the octets of the payload of each of the one or more ATM cells to a valid status to indicate that data is contained in the first subset of octets; and
setting the validity fields associated with the second subset of the octets of the payload of each of the one or more ATM cells to an invalid status to indicate that no data is contained in the second subset of octets; and
transmitting the one or more ATM cells across the ATM network;
wherein the transmission of the one or more ATM cells effectively results in transmission of the channelized circuit data at the arbitrary rate over the ATM network;
wherein the arbitrary rate is achieved by adjusting a ratio of a number of octets in the first subset of octets to a number of octets in the second subset of octets for each of the one or more ATM cells; and
wherein the arbitrary rate is not a multiple of a fundamental rate.
10. The method of claim 9 wherein the arbitrary rate is less than the fundamental rate.
11. The method of claim 9 wherein the arbitrary rate is higher than the fundamental rate.
12. A method for managing circuit emulation service over an Asynchronous Transfer Mode (ATM) network, the method comprising:
directing a first ATM processor to:
receive channelized circuit data, the channelized circuit data being transmitted at an arbitrary rate;
format the channelized circuit data into one or more ATM cells, each ATM cell having a payload, the payload having a plurality of octets and corresponding validity fields, each validity field being associated with one octet of the plurality of octets, the validity field indicating whether the associated octet contains valid data, wherein directing the first ATM processor to format the channelized circuit data into one or more ATM cells further comprises directing the first ATM processor to:
selectively include data in a first subset of the plurality of octets and not include data in a second subset of the plurality of octets of each ATM cell of the one or more ATM cells so that transmission of the one or more ATM cells results in transmission of the channelized circuit data at the arbitrary rate;
set the validity fields associated with the first subset of the octets of the payload of each of the one or more ATM cells to a valid status to indicate that data is contained in the first subset of octets; and
set the validity fields associated with the second subset of the octets of the payload of each of the one or more ATM cells to an invalid status to indicate that no data is contained in the second subset of octets; and
transmit the one or more ATM cells across the ATM network; and
directing a second ATM processor to receive and process the one or more ATM cells transmitted from the first ATM processor;
wherein the transmission of the one or more ATM cells effectively results in transmission of the channelized circuit data at the arbitrary rate over the ATM network;
wherein the arbitrary rate is achieved by adjusting a ratio of a number of octets in the first subset of octets to a number of octets in the second subset of octets for each of the one or more ATM cells; and
wherein the arbitrary rate is not a multiple of a fundamental rate.
13. The method of claim 12 further comprising:
directing the second ATM processor to process each ATM cell based on the validity fields and the associated octets contained therein;
wherein if a validity field indicates a “valid” status, the associated octet is considered to be containing valid data and will be processed, and if the validity field indicates an “invalid” status, the associated octet is considered to be containing invalid data and will not be processed; and
wherein by processing the one or more ATM cells based on the validity fields contained therein, the transmission of the one or more ATM cells effectively results in transmission of the channelized circuit data at the arbitrary rate over the ATM network.
14. The method of claim 12 wherein the arbitrary rate is less than the fundamental rate.
15. The method of claim 12 wherein the arbitrary rate is higher than the fundamental rate.