Method and apparatus for generating jitter test patterns on a high performance serial bus
View Patent ↗The present invention provides a computer readable medium containing instructions for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The instructions are executed to generate jitter test patterns by disabling the transmitter data scrambler of the second device; clear the port_error register of the device under test; and send a test pattern to said device under test.
1. A computer readable medium containing instructions, which, when executed by a computer, generate random jitter test patterns in a P1394b-compliant data communications system having a device under test operatively coupled to second device, by:
generating, by the second device, a sequence of maximum size asynchronous packets according to the P1394b standard; and
transmitting, by said second device, said sequence to the device under test.
2. The computer readable medium of claim 1 wherein said sequence comprises CURRENT_ASYNC requests, ignoring fairness.
3. The computer readable medium of claim 1 , wherein said sequence comprises a packet payload containing all zeros.
4. A computer readable medium containing instructions, which, when executed by a computer, generate jitter test patterns in a P1394b-compliant data communications system having a device under test operatively coupled to second device, the device under test having a port_error register and the second device having a data scrambler, by:
disabling the transmitter data scrambler of the second device;
clearing the port_error register of the device under test;
sending, by said second device, a test pattern to said device under test; and
reading the port_error register of the device under test.
5. The computer readable medium of claim 4 , wherein the error rate of a jitter test is determined by reading the port_error register.
6. The computer readable medium of claim 4 , wherein said test pattern comprises a sequence of at least 42 null packets followed by a packet containing at least 50 bytes of consecutive D21.5 symbols having an 8 bit data value AD 16 .
7. The computer readable medium of claim 6 , wherein said sequence of at least 42 null packets is generated by repeatedly issuing CURRENT_ASYNC requests and providing a zero length PHY packet.
8. The computer readable medium of claim 4 , wherein said test pattern comprises a single quadlet PHY packet containing the repeated data byte D30.3 having an 8 bit data value 0x7E.
9. The computer readable medium of claim 8 , wherein the total length of said test pattern is at least 167 symbols.
10. The computer readable medium of claim 4 , wherein said test pattern comprises two quadlet PHY packets containing the repeated data byte D30.3 having an 8 bit data value 0x7E.
11. The computer readable medium of claim 10 , wherein the total length of said test pattern is at least 167 symbols.