PCI express-compatible controller and interface for flash memory
View Patent ↗A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.
1. A method of performing an operation on a flash device, the operation being requested by a host separate from the flash device, the operation being PCI Express-compatible, the method comprising:
sending a first memory request from the host to the flash device, wherein the first memory request includes a command word setting in a header,
wherein the command word setting indicates the operation to be performed on the flash device, and
wherein the first memory request further includes memory mapped I/O addresses in the header, the memory mapped I/O addresses comprising a command word port and a data value port.
2. The method of claim 1 , wherein if the first memory request is a flash memory write operation, then further including:
sending a second memory request from the host to the flash device, wherein the second memory request includes a header and a data payload, wherein the data payload includes data to be written to the flash device.
3. The method of claim 2 , after receiving the second memory request, further including:
sending a message packet from the flash device to the host, wherein the message packet includes a header and a digest to report on a completion status of the write operation.
4. The method of claim 1 , wherein if the first memory request is a flash memory erase operation, then further including:
sending a second memory request from the host to the flash device, wherein the second memory request includes a header and a dummy data payload, wherein the dummy data payload includes dummy data to be written to the flash device.
5. The method of claim 4 , after receiving the second memory request, further including:
sending a message packet from the flash device to the host, wherein the message packet includes a header and a digest to report on a completion status of the write operation.
6. The method of claim 1 , wherein if the first memory request is a register write operation, then further including:
sending a second memory request from the host to the flash device, wherein the second memory request includes a header and a data payload, wherein the data payload includes data to be written to a register in the flash device.
7. The method of claim 6 , after receiving the second memory request, further including:
sending a message packet from the flash device to the host, wherein the message packet includes a header and a digest to report on a completion status of the write operation.
8. The method of claim 1 , wherein if the first memory request is a memory read operation, then further including:
sending a second memory request from the host to the flash device, wherein the second memory request includes a header and a digest, but no data payload.
9. The method of claim 8 , after receiving the second memory request, further including:
sending a completion packet from the flash device to the host if the read operation is successful, wherein the completion packet includes a header, data from the flash memory, and a digest; and
sending a message packet from the flash device to the host if the read operation is not successful, wherein the message packet includes a header and a digest to report on a completion status of the read operation.
10. The method of claim 1 , wherein if the first memory request is a status register read operation, then further including:
sending a second memory request from the host to the flash device, wherein the second memory request includes a header and a digest, but no data payload.
11. The method of claim 10 , after receiving the second memory request, further including:
sending a completion packet from the flash device to the host, wherein the completion packet includes a header, data from the status register, and a digest.
12. The method of claim 1 , wherein if the first memory request is a direct memory access (DMA) operation, then further including:
sending a second memory request from the flash device to the host.
13. The method of claim 12 , wherein if the DMA operation is a write, then the second memory request specifies a memory-read operation.
14. The method of claim 13 , further including the host:
releasing bus control after receiving the second memory request;
retrieving data requested in the second memory request; and
sending the flash device a completion packet with a data payload.
15. The method of claim 14 , further including the flash device:
issuing a write action; and
allowing data from the host to be written into flash memory.
16. The method of claim 9 , wherein if the DMA operation is a read, then the second memory request specifies a memory-write operation.
17. The method of claim 16 , wherein the second memory request includes a data payload.
18. The method of claim 17 , further including the host releasing bus control after receiving the second memory request.
19. The method of claim 18 , further including the host writing the data payload into system memory according to the second memory request.
20. The method of claim 19 , further including the host sending a message back to the flash device reporting on DMA status.