Array substrate for in-plane switching liquid crystal display device and method of fabricating the same with polycrystalline silicon pixel electrode
View Patent ↗An array substrate for in-plane switching liquid crystal display device includes a gate line on a substrate, a data line crossing the gate line to define a pixel region, a semiconductor layer including an active area and a source area, wherein the active area overlaps the gate line and the source area overlaps the data line, a drain electrode connected to the semiconductor layer, a first capacitor electrode in the pixel region and connected to the drain electrode, a pixel electrode connected to the first capacitor electrode and substantially in parallel to the data line, a common line substantially parallel to the gate line, a second capacitor electrode connected to the common line and overlapping the first capacitor electrode, and a common electrode connected to the common line and alternatively arranged with the pixel electrode, wherein the source area of the semiconductor layer, the drain electrode, the first capacitor electrode and the pixel electrode include doped polycrystalline silicon.
1. A method of fabricating an array substrate for an in-plane switching liquid crystal display device, comprising:
forming a semiconductor layer, a drain electrode, a first capacitor electrode and a pixel electrode on a substrate using polycrystalline silicon, the semiconductor layer including an active area and a source area;
forming a gate insulating layer, a gate line, a second capacitor electrode, a common line and a common electrode, wherein forming a gate insulating layer, a gate line, a second capacitor electrode, a common line and a common electrode include forming a first insulating layer and a first metal layer on the substrate including the semiconductor layer, the drain electrode, the first capacitor electrode and the pixel electrode and wherein forming the common electrode includes forming the common electrode to be alternatively arranged with the pixel electrode;
patterning the first insulating layer and the first metal layer, wherein the gate line overlaps the active area of the semiconductor layer, the second capacitor electrode covers the first capacitor electrode, and the common electrode extends from the common line;
forming an inter insulating layer to cover the gate line, the second capacitor electrode, the common line, and the common electrode by forming a second insulating layer and patterning the second insulating layer, the inter insulating layer having a source contact hole to expose the source area; and
forming a data line on the inter insulating layer, wherein forming a data line includes forming and patterning a second metal layer, the data line being connected to the source area through the source contact hole.
2. The method of claim 1 , wherein the source area of the semiconductor layer, the drain electrode, the first capacitor electrode and the pixel electrode include doped polycrystalline silicon.
3. The method of claim 2 , wherein the source area of the semiconductor layer, the drain electrode, the first capacitor electrode and the pixel electrode are one of n-type and p-type.
4. The method of claim 1 , wherein forming the semiconductor layer, the drain electrode, the first capacitor electrode and the pixel electrode includes masking the active area of the semiconductor layer and doping the source area of the semiconductor layer, the drain electrode, the first capacitor electrode and the pixel electrode.