Semiconductor device having multilayer interconnection structure and method for manufacturing the device

1. A semiconductor device having a multilayer interconnection structure, comprising:

a chip semiconductor substrate;

a plurality of interlayer insulating layers disposed on the chip semiconductor substrate;

a circuit section disposed on the chip semiconductor substrate;

a seal ring section comprising a seal ring structure; and

a plurality of walls of the seal ring structure that extend through the interlayer insulating layers and are arranged along a peripheral portion of the chip semiconductor substrate such that the walls surround the circuit section,

wherein the walls include upper sub-walls and lower sub-walls, the upper sub-walls extending through an interlayer insulating layer for an upper wiring layer, which is one of the interlayer insulating layers, and further extending into another interlayer insulating layer for a lower wiring layer adjacent to the upper wiring layer, and the lower sub-walls extend through the interlayer insulating layer for the lower wiring layer through which the upper sub-walls extending and connecting to the upper wiring layer such that lower portions of the upper wiring layers each extend into corresponding upper portions of the lower sub-walls.

2. The semiconductor device according to claim 1 , wherein the upper sub-walls are connected to the corresponding lower sub-walls such that the center of said upper sub-walls is misaligned with that of said lower sub-walls when viewed from above.

3. The semiconductor device according to claim 1 , wherein the walls comprise at least one of Al, Cu, and an alloy comprising at least one of Al and Cu as a major component.

4. The semiconductor device according to claim 1 , wherein the interlayer insulating layers include at least one sub-layers comprising at least one of SiO 2 , L-O x (ladder-type hydrosiloxane), HSQ, SiOC, SiLK(polyphenylene), SiOF, SiCN, SiC, SiN, and SiON.

5. The semiconductor device according to claim 1 , wherein the walls comprise at least one of a conductor placed in contact holes extending through the corresponding interlayer insulating layers and a conductor that is placed in the contact holes extending through the corresponding interlayer and placed in grooves, connected to the contact holes, comprising an aperture area larger than that of the contact holes.

6. The semiconductor device according to claim 1 , wherein the plurality of walls comprise at least one of Al, Cu, and an alloy comprising at least one of Al and Cu as a major component.

7. The semiconductor device according to claim 1 , wherein the interlayer insulating layers comprise at least one sub-layer comprising at least one of SiO 2 , L-O x (ladder-type hydrosiloxane), HSQ, SiOC, SiLK(polyphenylene), SiOF, SiCN, SiC, and SiON.

8. The semiconductor device according to claim 1 , wherein said upper sub-walls comprise sealing wires.

9. The semiconductor device according to claim 1 , wherein said lower sub-walls comprise via contacts.

10. The semiconductor device according to claim 1 , wherein the semiconductor device comprises a single-damascene structure.

11. The semiconductor device according to claim 1 , wherein the semiconductor device comprises a double-damascene structure.

12. The semiconductor device according to claim 1 , wherein said plurality of walls comprise sealing wires that extend across interfaces between said interlayer insulating layers and stopper layers.

13. The semiconductor device according to claim 1 , wherein said upper sub-walls and said lower sub-walls extend across an interface between said interlayer insulating layers and a stopper layer.

14. The semiconductor device according to claim 1 , wherein said upper sub-walls and said lower sub-walls overlap.

15. The semiconductor device according to claim 14 , wherein said upper sub-walls and said lower sub-walls overlap across a contact point of said plurality of interlayer insulating layers and a stopping layer.

16. A semiconductor device having a multilayer interconnection structure, comprising:

a chip semiconductor substrate;

a plurality of interlayer insulating layers disposed on the chip semiconductor substrate;

a circuit section disposed on the chip semiconductor substrate; and

a seal ring section comprising a seal ring structure;

wherein a plurality of walls of the seal ring structure that extend through the interlayer insulating layers and are arranged along a peripheral portion of the chip semiconductor substrate such that the walls surround the circuit section, and an interface between an upper wiring layer and a lower wiring layer being adjacent to the upper wiring layer has a portion which is not on the same plan as an interface between an interlayer insulating layer for the upper wiring layer and another interlayer insulating layer for the lower wiring layer in the seal ring section.

17. A method for manufacturing a semiconductor device, comprising:

forming a plurality of interlayer insulating layers on a substrate; and

forming a plurality of walls of a seal ring structure that extend through the interlayer insulating layers and surround circuit sections in such a manner that the walls are joined to one another,

wherein the walls include upper sub-walls and lower sub-walls, the upper sub-walls extending through an interlayer insulating layer for an upper layer, which is one of the interlayer insulating layers, and further extending into another interlayer insulating layer for a lower layer adjacent to the upper layer, and the lower sub-walls extending through the interlayer insulating layer for the lower layer through which the upper sub-walls extend and connecting to the upper layer such that lower portions of the upper layers each extend into corresponding upper portions of the lower sub-walls.

18. The method for manufacturing a semiconductor device according to claim 17 , wherein the upper sub-walls are connected to the corresponding lower sub-walls such that a center of the upper sub-walls is misaligned with that of the lower sub-walls when viewed from above.