IP Library Granted Patent US 7,024,440
Granted Patent B2
US 7,024,440 · App. 10/806,094 · Granted Apr 4, 2006

Method and system for processing a discrete time input signal where the clock rate of a discrete time output signal is a multiple of the clock rate of input signal samples

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Quick Facts
Patent No.
US 7,024,440
App. No.
10/806,094
Granted
Apr 4, 2006
Kind
B2
Abstract

A method and system of efficiently processing a discrete time input signal having a plurality of input signal samples that occur at a first clock rate into a discrete time output signal having a second clock rate that is R times the first clock rate is presented. The method includes receiving the input signal and filtering the input signal with an N-taps finite impulse response (FIR) filter having N filter coefficients. The method reduces the number of required operations and reduces computational errors in the filtering and interpolation of discrete input signals.

Claims (92)

1. A method of efficiently processing a discrete time input signal having a plurality of input signal samples that occur at a first clock rate into a discrete time output signal having a second clock rate that is R times the first clock rate, the method comprising the steps of:

receiving the input signal; and

filtering the input signal with an N-taps finite impulse response (FIR) filter having N filter coefficients according to

i

=

k

ceil

[

(

N

+

1

-

k

)

/

R

]

-

1

b

iR

-

k

u

(

(

m

-

i

+

k

)

T

s

)

wherein b iR−k is one of the N filter coefficients, u((m−i+k)T s ) is one of the input signal samples, T s is a slow clock sampling period, m equals (0, 1, 2, 3, . . . ), and k equals (0, 1, 2, . . . , R−1).

2. The method of claim 1 , wherein the input signal is a position signal.

3. The method of claim 1 , wherein each of the N filter coefficients is the result of a discrete convolution of a series of FIR filters.

4. The method of claim 1 , wherein the output signal is sent to a control system that controls a photolithography scanning operation.

5. A system for efficiently processing a discrete time input signal having a plurality of input signal samples that occur at a first clock rate into a discrete time output signal having a second clock rate that is R times the first clock rate, the system comprising:

means for receiving the input signal; and

means for filtering the input signal with an N-taps finite impulse response (FIR) filter having N filter coefficients according to

i

=

k

ceil

[

(

N

+

1

-

k

)

/

R

]

-

1

b

iR

-

k

u

(

(

m

-

i

+

k

)

T

s

)

wherein b iR−k is one of the N filter coefficients, u((m−i+k)T s ) is one of the input signal samples, T s is a slow clock sampling period, m equals (0, 1, 2, 3, . . . ), and k equals (0, 1, 2, . . . , R−1).

6. The system of claim 5 , wherein the input signal is a position signal.

7. The system of claim 5 , wherein each of the N filter coefficients is the result of a discrete convolution of a series of FIR filters.

8. The system of claim 5 , wherein the output signal is sent to a control system that controls a photolithography scanning operation.

Assignments (3)
CERTIFICATE OF CONVERSION Recorded Oct 21, 2004
From: ASML US, INC.
To: ASML US, LLC
Reel/Frame 015273/0682 →
MERGER Recorded Oct 21, 2004
From: ASML US, LLC; ASM LITHOGRAPHY, INC.
To: ASML US, INC.
Reel/Frame 015273/0685 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2004
From: WIENER, ROBERTO B.; SILICON VALLEY GROUP, INC. (CHANGE OF NAME); ASML US, INC. (MERGER); ASML US, INC. (CONFIRMATORY ASSIGNMENT)
To: ASML HOLDING N.V.
Reel/Frame 015130/0105 →