IP Library Granted Patent US 7,085,793
Granted Patent B2
US 7,085,793 · App. 10/806,325 · Granted Aug 1, 2006

Method and system for efficient and accurate processing of a discrete time input signal

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Quick Facts
Patent No.
US 7,085,793
App. No.
10/806,325
Granted
Aug 1, 2006
Kind
B2
Abstract

A method and system of accurately processing a discrete time input signal having a first clock rate into a discrete time output signal having a second clock rate is presented. The method includes delta filtering the input signal to produce an intermediate signal having the first clock rate and delta interpolating the intermediate signal to produce the output signal. Delta filtering includes calculating an input delta signal by subtracting an initial value from the input signal, generating a filtered delta signal, and adding the initial value to the filtered delta signal. Delta interpolating includes upsampling the intermediate signal to the second clock rate, calculating an upsampled intermediate delta signal by subtracting an initial value from the upsampled intermediate signal, filtering the intermediate delta signal, and adding the initial value to the filtered intermediate delta signal. The method reduces the number of required operations and reduces computational errors in the filtering and interpolation of discrete input signals.

Claims (38)

1. A method of accurately processing a discrete time input signal, p(n), having a first clock rate into a discrete time output signal having a second clock rate, comprising the steps of:

delta filtering the input signal to produce an intermediate signal having the first clock rate; and

delta interpolating the intermediate signal to produce the output signal,

whereby computational errors are minimized.

2. The method of claim 1 , wherein said delta filtering step comprises:

calculating an input delta signal, d(n), according to d(n)=p(n)−p i , wherein p i is an initial value of p(n);

generating a filtered delta signal f(n) from d(n); and

adding p i to f(n), thereby generating the intermediate signal.

3. The method of claim 2 , wherein said generating step comprises the step of generating a finite impulse response (FIR) filtered delta signal f(n) from d(n).

4. The method of claim 1 , wherein said delta interpolating step comprises the steps of:

upsampling the intermediate signal to the second clock rate;

calculating an upsampled intermediate delta signal, u(n), according to u(n)=i(n)−p i , wherein i(n) is the upsampled intermediate signal and p i is an initial value of p(n);

generating a filtered intermediate delta signal g(n) from u(n); and

adding p i to g(n), thereby generating the output signal.

5. The method of claim 4 , wherein said generating step comprises the step of generating a finite impulse response (FIR) filtered intermediate delta signal g(n) from u(n).

6. The method of claim 5 , wherein said generating step comprises the step of generating a Lagrange finite impulse response (FIR) filtered intermediate delta signal g(n) from u(n).

7. The method of claim 1 , wherein the second clock rate is an integer multiple of the first clock rate.

8. The method of claim 1 , wherein the input signal is a position signal.

9. The method of claim 1 , wherein the output signal is sent to a control system that controls a photolithography scanning operation.

10. A system for accurately processing a discrete time input signal, p(n), having a first clock rate into a discrete time output signal having a second clock rate, comprising:

means for delta filtering the input signal to produce an intermediate signal having the first clock rate; and

means for delta interpolating the intermediate signal to produce the output signal,

whereby computational errors are minimized.

11. The system of claim 10 , wherein said delta filtering means comprises:

means for calculating an input delta signal, d(n), according to d(n)=p(n)−p i , wherein p i is an initial value of p(n);

means for generating a filtered delta signal j(n) from d(n); and

means for adding p i to f(n), thereby generating the intermediate signal.

12. The system of claim 11 , wherein said generating means comprises means for generating a finite impulse response (FIR) filtered delta signal f(n) from d(n).

13. The system of claim 10 , wherein said delta interpolating means comprises:

means for upsampling the intermediate signal to the second clock rate;

means for calculating an upsampled intermediate delta signal, u(n), according to u(n)=i(n)−p i , wherein i(n) is the upsampled intermediate signal and p i is an initial value of p(n);

means for generating a filtered intermediate delta signal g(n) from u(n); and

means for adding p i to g(n), thereby generating the output signal.

14. The system of claim 13 , wherein said generating means comprises means for generating a finite impulse response (FIR) filtered intermediate delta signal g(n) from u(n).

15. The system of claim 14 , wherein said generating means comprises means for generating a Lagrange finite impulse response (FIR) filtered intermediate delta signal g(n) from u(n).

16. The system of claim 10 , wherein the second clock rate is an integer multiple of the first clock rate.

17. The system of claim 10 , wherein the input signal is a position signal.

18. The system of claim 10 , wherein the output signal is sent to a control system that controls a photolithography scanning operation.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2004
From: WIENER, ROBERTO B.
To: SILICON VALLEY GROUP, INC.
Reel/Frame 015273/0665 →
CERTIFICATE OF CONVERSION Recorded Oct 21, 2004
From: ASML US, INC.
To: ASML US, LLC
Reel/Frame 015273/0682 →
MERGER Recorded Oct 21, 2004
From: ASML US, LLC; ASM LITHOGRAPHY, INC.
To: ASML US, INC.
Reel/Frame 015273/0685 →
CHANGE OF NAME Recorded Oct 21, 2004
From: SILICON VALLEY GROUP, INC.
To: ASML US, INC.
Reel/Frame 015273/0696 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2004
From: ASML US, INC.
To: ASML HOLDING N.V.
Reel/Frame 015273/0702 →