I/O buffer with wide range voltage translator
View Patent ↗In accordance with an aspect of an input/output device for providing fast translation between differential signals from a core of an integrated circuit and higher voltage signals that are external to the core, an I/O buffer includes low voltage devices for receiving core input signals, a cascode stage for setting a bias between the input devices and an output stage, and an output stage including a current mirror for providing a translated external output. Another aspect of the invention further includes a feedback path to cut off the current mirror to prevent static current and a keeper device to maintain an output level after cut off of the current mirror.
1. An input/output signaling apparatus, comprising:
a low voltage input stage that receives low voltage core input signals;
an output stage that provides a higher voltage external output based on the low voltage core input signals;
a cascode stage coupled between the low voltage input stage and the output stage that provides a bias to the output stage and provides a limit for preventing breakdown in the low voltage input stage;
a feedback device coupled to the output stage that prevents static current after a change in value of the external output; and
a keeper device that maintains the changed value of the external output based on operation of the feedback device.
2. The input/output signaling apparatus of claim 1 , wherein a range of the low voltage core input signals is limited to between approximately 0 volt and 1 volt.
3. The input/output signaling apparatus of claim 1 , wherein a range of the higher voltage external output can exceed a range of the low voltage core input signals by a factor of approximately three.
4. The input/output signaling apparatus of claim 2 , wherein a range of the higher voltage external output can exceed the range of the low voltage core input signals by a factor of approximately three.
5. The input/output signaling apparatus of claim 4 , wherein the range of the higher voltage external output is between approximately 0 volt and 3.3 volts.
6. The input/output signaling apparatus of claim 5 , wherein the low voltage input stage is comprised of a pair of low-voltage transistors having gates respectively coupled to a pair of differential signals corresponding to the low voltage core input signals.
7. The input/output signaling apparatus of claim 5 , wherein the output stage is a current mirror comprised of a pair of transistors having threshold voltages in accordance with the higher voltage external output.
8. The input/output signaling apparatus of claim 7 , wherein the cascade stage is comprised of a pair of transistors having threshold voltages approximately the same as the threshold voltages of the current mirror transistors.
9. The input/output signaling apparatus of claim 5 , wherein the low voltage input stage is comprised of a first pair of low-voltage transistors having gates respectively coupled to a pair of differential signals corresponding to the low voltage core input signals, and
wherein the output stage is a current mirror comprised of a second pair of transistors having threshold voltages in accordance with the higher voltage external output, and
wherein the cascode stage is comprised of a third pair of transistors having threshold voltages approximately the same as the threshold voltages of the current mirror transistors.
10. The input/output signaling apparatus of claim 1 , wherein the low voltage input stage is comprised of a pair of low-voltage transistors having gates respectively coupled to a pair of differential signals corresponding to the low voltage core input signals.
11. The input/output signaling apparatus of claim 1 , wherein the output stage is a current mirror comprised of a pair of transistors having threshold voltages in accordance with the higher voltage external output.
12. The input/output signaling apparatus of claim 11 , wherein the cascade stage is comprised of a pair of transistors having threshold voltages approximately the same as the threshold voltages of the current mirror transistors.
13. The input/output signaling apparatus of claim 1 , wherein the low voltage input stage is comprised of a first pair of low-voltage transistors having gates respectively coupled to a pair of differential signals corresponding to the low voltage core input signals, and
wherein the output stage is a current minor comprised of a second pair of transistors having threshold voltages in accordance with the higher voltage external output, and
wherein the cascade stage is comprised of a third pair of transistors having threshold voltages approximately the same as the threshold voltages of the current mirror transistors.
14. An input/output signaling apparatus, comprising:
a low voltage input stage that receives low voltage core input signals;
an output stage that provides a higher voltage external output based on the low voltage core input signals;
a cascode stage coupled between the low voltage input stage and the output stage that provides a bias to the output stage;
a feedback device coupled to the output stage; and
a keeper device that maintains a changed value of the external output based on operation of the feedback device.
15. The input/ output signaling apparatus of claim 14 , wherein a range of the low voltage core input signals is limited to between approximately 0 volt and 1 volt.
16. The input/output signaling apparatus of claim 15 , wherein a range of the higher voltage external output can exceed the range of the low voltage core input signals by a factor of approximately three.
17. The input/output signaling apparatus of claim 16 , wherein the range of the higher voltage external output is between approximately 0 volt and 3.3 volts.
18. The input/output signaling apparatus of claim 14 , wherein a range of the higher voltage external output can exceed a range of the low voltage core input signals by a factor of approximately three.
19. The input/output signaling apparatus of claim 14 , wherein the bias provided to the output stage provides a limit for preventing breakdown in the low voltage input stage.
20. The input/ output signaling apparatus of claim 14 , wherein the feedback device prevents static current after a change in value of the external output.
21. A method for input/output signaling, the method comprising the steps of:
receiving low voltage core input signals;
providing a higher voltage external output based on the low voltage core input signals;
providing a bias to the external output;
providing a feedback signal, the feedback signal relating to a change in value of the external output; and
maintaining the changed value of the external output based on the feedback signal.
22. The method of claim 21 , wherein a range of the low voltage core input signals is limited to between approximately 0 volt and 1 volt and the range of the higher voltage external output is between approximately 0 volt and 3.3 volts.
23. The method of claim 21 , wherein the bias provides a limit for preventing breakdown in the step of receiving the low voltage core input signals.
24. The method of claim 21 , wherein the feedback signal prevents static current after the changed value of the external output.