IP Library Granted Patent US 7,403,576
Granted Patent B2
US 7,403,576 · App. 10/810,410 · Granted Jul 22, 2008

Systems and methods for receiving data in a wireless communication network

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,403,576
App. No.
10/810,410
Granted
Jul 22, 2008
Kind
B2
Abstract

A method of communicating over a wideband communication channel divided into a plurality of sub-channels comprises dividing a single serial message intended for one of the plurality of communication devices into a plurality of parallel messages, encoding each of the plurality of parallel messages onto at least some of the plurality of sub-channels, and transmitting the encoded plurality of parallel messages to the communication device over the wideband communication channel.

Claims (10)

1. A radio receiver, comprising: a band pass filter configured to filter a combined signal; a clocked comparator coupled with the band pass filter, the clocked comparator configured to compare the filter combined signal to a ground reference when the comparator is enabled by a clock signal; a digital-to-analog converter coupled with the clocked comparator, the digital-to-analog converter configured to convert the output of the clocked comparator to an analog signal; and a combiner configured to receive a RF signal and combine the RF signal with the analog signal generated by the digital-to-analog converter in order to generate the combined signal; and a plurality of clocked comparators coupled to the band pass filter, each of the clocked comparators configured to be activated on a different phase of a clock signal and a combiner coupled to the plurality of clocked comparators, the combiner configured to combine the outputs of the clocked comparators.

2. The radio receiver of claim 1 , further comprising filtering and decimation circuitry configured to filter and decimate the output of the clocked comparator.

3. The radio receiver of claim 1 , further comprising a clock signal configured to clock the clocked comparator at a rate required to achieve a selected effective number of bits at the output of the filtering and decimation circuitry.

4. The radio receiver of claim 1 , wherein the combiner is a passive combiner.

5. The radio receiver of claim 1 , wherein the digital-to-analog converter is coupled to the plurality of clocked comparators via the combiner.

6. A receiver, comprising: an antenna configured to receive a RF signal; a filter coupled to the antenna, the filter configured to filter the received RF signal; an amplifier coupled with the filter, the amplifier configured to amplify the filtered RF signal; and a radio receiver, comprising: a band pass filter configured to filter a combined signal; a plurality of clocked comparators coupled with the band pass filter, the clocked comparators configured to compare the filter combined signal to a ground reference when each comparator is enabled by a clock signal, and wherein each of the clocked comparators is configured to be activated on a different phase of the clock signal; a combiner coupled to the plurality of clocked comparators, the combiner configured to combine the outputs of the clocked comparators; a digital-to-analog converter coupled with the clocked comparators), the digital-to-analog converter configured to convert the output of the clocked comparators to an analog signal; and a combiner configured to receive the amplified and filtered RF signal and combine the amplified and filtered RF signal with the analog signal generated by the digital-to-analog converter in order to generate the combined signal.

7. The receiver of claim 6 , wherein the radio receiver further comprises filtering and decimation circuitry configured to filter and decimate the output of the clocked comparator.

8. The receiver of claim 6 , wherein the radio receiver further comprises a clock signal configured to clock the clocked comparator at a rate required to achieve a selected effective number of bits at the output of the filtering and decimation circuitry.

9. The receiver of claim 6 , wherein the combiner is a passive combiner.

10. The receiver of claim 6 , wherein the digital-to-analog converter is coupled to the plurality of clocked comparators via the combiner.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Oct 17, 2020
From: AUDIO MPEG, INC.
To: PULSE-LINK, INC.
Reel/Frame 054086/0652 →
MERGER Recorded Dec 31, 2015
From: INTELLECTUAL VENTURES HOLDING 73 LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 037408/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNORS PREVIOUSLY RECORDED ON REEL 020702 FRAME 0746. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNORS INTEREST. Recorded May 3, 2012
From: LAKKIS, ISMAIL; WIDEBAND ACCESS INC.
To: PULSE-LINK, INC.
Reel/Frame 028147/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2012
From: PULSE-LINK, INC.
To: INTELLECTUAL VENTURES HOLDING 73 LLC
Reel/Frame 027910/0936 →
SECURITY AGREEMENT Recorded Apr 22, 2009
From: PULSE~LINK, INC.
To: AUDIO MPEG, INC.
Reel/Frame 022575/0704 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2008
From: LAKKIS, ISMAIL
To: PULSE-LINK, INC.
Reel/Frame 020702/0746 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2004
From: LAKKIS, ISMAIL
To: WIDEBAND ACCESS, INC.
Reel/Frame 015679/0056 →