Method and/or architecture implemented in hardware for the adjustment of messages with indeterministic length
View Patent ↗An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data output signal in response to a data input signal, a valid word signal, and a select signal. The second circuit may be configured to generate the select signal in response to the valid word signal, a start of frame signal, and end of frame signal and the data output signal. The select signal may adjust a starting point of each of the words to match a starting point of the first word.
1. An apparatus comprising:
a first circuit configured to generate a data output signal in response to (i) a data input signal comprising a series of words, (ii) a valid word signal, and (iii) a select signal; and
a second circuit configured to generate said select signal in response to (i) said valid word signal, (ii) a start of frame signal, (iii) an end of frame signal and (iv) said data output signal, wherein (a) said select signal adjusts a starting point of each of said words to match a starting point of said first word and (b) said second circuit comprises (i) a decoder configured to present a length signal in response to said data output signal, (ii) a subtractor configured to present a sum signal in response to said length signal and a first enable signal and (iii) an adder circuit configured to generate said select signal in response to said sum signal.
2. The apparatus according to claim 1 , wherein said second circuit generates said select signal in further response to a clock signal.
3. The apparatus according to claim 1 , wherein said first circuit comprises a data circuit and said second circuit comprises a control circuit.
4. The apparatus according to claim 1 , wherein said first circuit comprises:
a first and a second register configured to arrange one or more bits of said data input signal; and
a multiplexer circuit configured to present said data output signal in response to said arranged bits.
5. The apparatus according to claim 4 , wherein said second register includes a data input configured to receive an output of said first register.
6. The apparatus according to claim 4 , wherein said first register and said second register are configured to receive said valid word signal.
7. The apparatus according to claim 1 , wherein said data input signal, said valid word signal, said start of frame signal and said end of frame signal are received from a data source.
8. The apparatus according to claim 1 , wherein said second circuit further comprises a finite state machine configured to control said subtractor and said adder.
9. The apparatus according to claim 8 , wherein said second circuit further comprises:
a sum circuit configured to process said sum signal before said adder circuit generates said select signal.
10. The apparatus according to claim 9 , wherein said sum circuit presents an end message signal to said finite state machine.
11. A method for adjusting messages in hardware comprising:
(A) generating a data output signal in response to (i) a data input signal comprising a series of words, (ii) a valid word signal, and (iii) a select signal; and
(B) generating said select signal in response to (i) said valid word signal, (ii) a start of frame signal, (iii) an end of frame signal and (iv) said data output signal, wherein (a) said select signal adjusts a starting point of each of said words to match a starting point of said first word and said method generates said select signal using (i) a decoder configured to present a length signal in response to said data output signal, (ii) a subtractor configured to present a sum signal in response to said length signal and a first enable signal and (iii) an adder circuit configured to generate said select signal in response to said sum signal.
12. An apparatus comprising:
means for generating a data output signal in response to (i) a data input signal comprising a series of words, (ii) a valid word signal, and (iii) a select signal; and
means for generating said select signal in response to (i) said valid word signal, (ii) a start of frame signal, (iii) an end of frame signal and (iv) said data output signal, wherein (a) said select signal adjusts a starting point of each of said words to match a starting point of said first word and said apparatus generates said select signal using (i) a decoder configured to present a length signal in response to said data output signal, (ii) a subtractor configured to present a sum signal in response to said length signal and a first enable signal and (iii) an adder circuit configured to generate said select signal in response to said sum signal.