Liquid crystal display and thin film transistor array panel therefor
View Patent ↗A gate line extending in a transverse direction and a data line intersecting the gate line are formed on the substrate. A pixel electrode connected to the gate line and the data line through a thin film transistor is formed on an insulating layer. The pixel electrode has a cutout and a protrusion is disposed in the cutout. Another protrusion is disposed on the data line.
1. A thin film transistor array panel, comprising:
a substrate;
a gate line formed on the substrate and including a gate electrode;
a gate insulating layer formed on the gate line;
a semiconductor layer formed on the gate insulating layer;
a data line formed at least in part on the semiconductor layer;
a drain electrode formed on the semiconductor layer at least in part and separated from the data line;
a first passivation layer formed on the data line and the drain electrode;
a first protrusion formed directly on at least a portion of the first passivation layer and disposed on a portion corresponding to the data line;
a pixel electrode formed directly on the first passivation layer and connected to the drain electrode, the pixel electrode including a cutout, and
a second protrusion disposed on the cutout.
2. The thin film transistor array panel of claim 1 , further comprising a storage electrode line overlapping the pixel electrode.
3. The thin film transistor array panel of claim 2 , wherein the storage electrode line comprises an expansion overlapping the drain electrode.
4. The thin film transistor array panel of claim 2 , wherein the storage electrode line comprises a branch overlapping the cutout.
5. A thin film transistor array panel, comprising:
a substrate;
a gate line formed on the substrate and including a gate electrode;
a gate insulating layer formed on the gate line;
a semiconductor layer formed on the gate insulating layer;
a data line formed at least in part on the semiconductor layer;
a drain electrode formed on the semiconductor layer at least in part and separated from the data line;
a first passivation layer formed on the data line and the drain electrode and having a contact hole exposing the drain electrode at least in part;
a pixel electrode formed directly on the first passivation layer and connected to the drain electrode through the contact hole, the pixel electrode having a cutout; and
a protrusion formed directly on at least a portion of the first passivation layer and disposed in the cutout at least in part.
6. The thin film transistor array panel of claim 5 , further comprising a storage electrode line overlapping the pixel electrode.
7. The thin film transistor array panel of claim 6 , wherein the storage electrode line comprises an expansion overlapping the drain electrode.
8. The thin film transistor array panel of claim 6 , wherein the storage electrode line comprises a branch overlapping the cutout.
9. The thin film transistor array panel of claim 5 , further comprising a spacer having a height larger than the protrusion and disposed on the same layer as the protrusion.
10. The thin film transistor array panel of claim 9 , wherein the protrusion and the spacer comprise organic material.
11. The thin film transistor array panel of claim 5 , comprising a color filter disposed between the first passivation layer, and the protrusion and the pixel electrode.
12. The thin film transistor array panel of claim 11 , further comprising a second passivation layer formed on the color filter and intermediate to the protrusion and the pixel electrode.
13. The thin film transistor array panel of claim 5 , wherein the semiconductor layer has substantially the same planar shape as the data line and the drain electrode.