Digital modulator employing a polyphase up-converter structure
View Patent ↗An upconverting circuit is disclosed. The upconverting circuit includes a polyphase component generator that provides N p polyphase components at each input polyphase cycle, wherein N p >2 on each input polyphase cycle defined by a clock. A memory stores the polyphase components from at least one polyphase cycle prior to the current polyphase cycle. A plurality of filters process the polyphase components stored in the memory. Each filter processes a plurality of the polyphase components to generate a filtered polyphase component corresponding to that filter. A multiplexer outputs the filtered polyphase components in a predetermined order to generate a filtered output signal. In one embodiment, each filter utilizes the same functional relationship to generate the filtered polyphase components. In another embodiment, the memory is a shift register. The filters can be of arbitrary complexity.
1. An upconverting circuit comprising:
a clock for defining a sequence of input polyphase cycles;
a polyphase component generator that provides 2N p polyphase components from an input signal having an in-phase and a quadrature signal at each input polyphase cycle, wherein N p >2, there being N p polyphase components corresponding said in-phase signal and N p polyphase components corresponding to said quadrature signal;
a memory that stores said polyphase components from at least one polyphase cycle prior to the current polyphase cycle;
a plurality of filters, each filter processing a plurality of said polyphase components stored in said memory to generate a filtered polyphase component corresponding to that filter, wherein in any given input polyphase cycle, at least one of said filters processes a plurality of different polyphase components stored in said memory from a corresponding polyphase cycle; and
a multiplexer that outputs said filtered polyphase components in a predetermined order to generate a filtered output signal comprising an upconverted version of said input signal.
2. The upconverting circuit of claim 1 wherein each filter utilizes the same functional relationship to generate said filtered polyphase components.
3. The upconverting circuit of claim 1 wherein said filters are finite impulse response filters.
4. The upconverting circuit of claim 1 wherein said polyphase component generator receives one pair of digital signals in each polyphase cycle.
5. An upconverting circuit comprising:
a clock for defining a sequence of input polyphase cycles;
a polyphase component generator that provides N p polyphase components at each input polyphase cycle, wherein N p >2;
a memory that stores said polyphase components from at least one polyphase cycle prior to the current polyphase cycle;
a plurality of filters, each filter processing a plurality of said polyphase components stored in said memory to generate a filtered polyphase component corresponding to that filter; and
a multiplexer that outputs said filtered polyphase components in a predetermined order to generate a filtered output signal;
wherein said memory comprises a shift register.
6. An upconverting circuit comprising:
a clock for defining a sequence of input polyphase cycles;
a polyphase component generator that provides N p polyphase components at each input polyphase cycle, wherein N p >2;
a memory that stores said polyphase components from at least one polyphase cycle prior to the current polyphase cycle;
a plurality of filters, each filter processing a plurality of said polyphase components stored in said memory to generate a filtered polyphase component corresponding to that filter; and
a multiplexer that outputs said filtered polyphase components in a predetermined order to generate a filtered output signal;
wherein said filter generate a filtered polyphase component that depends on a non-linear combination of said polyphase component.