Two-wire interface in which a master component monitors the data line during the preamble generation phase for synchronization with one or more slave components

1. In a system that includes a master component that is configured to communicate with one or more slave components over a clock wire and a data wire, a method for the master component to communicate over the data wire while enabling recovery of synchronization between the master component and the one or more slave components, the method comprising:

determining that an operation is to be performed on a slave component of the one or more slave components;

monitoring the data wire of the two-wire interface upon determining that the operation is to be performed on the slave component;

detecting at least a predetermined number “n” of consecutive bits of the same binary polarity that have occurred on the data wire while monitoring the data wire, the predetermined number of consecutive bits comprising a preamble of a frame, the preamble being automatically asserted on the data wire without the master component or the slave component needing to affirmatively assert the preamble on the data wire;

transmitting a three bit operational code designating an operation state and a structure of the frame;

dynamically adjusting the structure of the frame based at least partially on bandwidth available; and

transmitting non-preamble portions of the frame over the data wire with guaranteed bits unconditionally inserted in predetermined bit positions that are positioned at least every “n” consecutive bit positions in the non-preamble portions of the frame, each predetermined bit position being offset a predetermined number of consecutive bit positions from the last bit position of the preamble, the guaranteed bits being opposite in polarity with respect to the preamble bits' polarity.

2. A method in accordance with claim 1 , wherein the two-wire interface is a guaranteed header two-wire interface.

3. A method in accordance with claim 1 , wherein the two-wire interface is not a guaranteed header two-wire interface.

4. A method in accordance with claim 1 , wherein detecting at least the predetermined number of consecutive bits comprises:

detecting at least the predetermined number of consecutive bits of a logical one.

5. A method in accordance with claim 4 , wherein the data wire is pulled high when no components are asserting binary values on the data wire.

6. A method in accordance with claim 1 , wherein detecting at least the predetermined number of consecutive bits comprises:

detecting at least the predetermined number of consecutive bits of a logical zero.

7. A method in accordance with claim 6 , wherein the data wire is pulled low when no components are asserting binary values on the data wire.

8. A method in accordance with claim 1 , further comprising:

asserting, at the master component, a clock signal on the clock wire during at least some of the act of monitoring the data wire.

9. A method in accordance with claim 1 , further comprising:

asserting, at the master component, a voltage level on the data wire during only a portion of the act of monitoring the data wire.

10. A method in accordance with claim 9 , wherein the data wire is pulled high when no components are asserting binary values on the data wire.

11. A method in accordance with claim 9 , wherein the data wire is pulled low when no components are asserting binary values on the data wire.

12. A method in accordance with claim 1 , further comprising:

refraining from asserting, at the master component, a voltage level on the data wire while monitoring the data wire.

13. A method in accordance with claim 12 , wherein the data wire is pulled high when no components are asserting binary values on the data wire.

14. A method in accordance with claim 12 , wherein the data wire is pulled low when no components are asserting binary values on the data wire.

15. A method in accordance with claim 1 , wherein determining that an operation is to be performed on a slave component of the one or more slave components comprises:

determining that a read operation is to be performed with an extended address as compared to other frames communicated over the data wire.

16. A method in accordance with claim 1 , wherein determining that an operation is to be performed on a slave component of the one or more slave components comprises:

determining that a write operation is to be performed with an extended address as compared to other frames communicated over the data wire.

17. A method in accordance with claim 1 , wherein determining that an operation is to be performed on a slave component of the one or more slave components comprises:

determining that a read operation is to be performed with a shorter address as compared to other frames communicated over the data wire.

18. A method in accordance with claim 1 , wherein determining that an operation is to be performed on a slave component of the one or more slave components comprises:

determining that a write operation is to be performed with a shorter address as compared to other frames communicated over the data wire.

19. A method in accordance with claim 1 , wherein determining that an operation is to be performed on a slave component of the one or more slave components comprises:

determining that a read operation is to be performed with cyclic redundancy checking over the data wire.

20. A method in accordance with claim 1 , wherein determining that an operation is to be performed on a slave component of the one or more slave components comprises:

determining that a write operation is to be performed with cyclic redundancy checking over the data wire.

21. A method in accordance with claim 1 , wherein determining that an operation is to be performed on a slave component of the one or more slave components comprises:

determining that a read operation is to be performed with acknowledgements over the data wire.

22. A method in accordance with claim 1 , wherein determining that an operation is to be performed on a slave component of the one or more slave components comprises:

determining that a write operation is to be performed with acknowledgements over the data wire.

23. A method in accordance with claim 1 , wherein the predetermined number “n” of consecutive bits is 15 bits.

24. A method in accordance with claim 1 , further comprising determining, as a direct consequence of detecting the preamble on the data wire, that the slave component is not transmitting over the data wire and that it is safe for the master component to transmit over the data wire.

25. A method in accordance with claim 1 , wherein the number of bits in the non-preamble portions of the frame is at least double the predetermined number “n” of bits in the preamble.

26. A method in accordance with claim 1 , wherein the structure of the frame includes whether the frame includes an extended field.

27. A system comprising:

a master component;

a slave component;

a clock wire interconnected between the master component and the slave component;

a data wire interconnected between the master component and the slave component,

wherein the master component is configured to perform:

determining that an operation is to be performed on the slave component;

monitoring the data wire of the two-wire interface upon determining that the operation is to be performed on the slave component;

detecting at least a predetermined number “n” of consecutive bits of the same binary polarity that have occurred on the data wire while monitoring the data wire, the predetermined number of consecutive bits comprising a preamble of a frame;

determining, as a direct consequence of detecting the preamble on the data wire, that the slave component is not transmitting over the data wire and that it is safe for the master component to transmit over the data wire;

transmitting non-preamble portions of the frame over the data wire with guaranteed bits unconditionally inserted in predetermined bit positions that are positioned at least every “n” consecutive bit positions in the non-preamble portions of the frame, each predetermined bit position being offset a predetermined number of consecutive bit positions from the last bit position of the preamble, the guaranteed bits being opposite in polarity with respect to the preamble bits' polarity; and

further transmitting in the non-preamble portions of the frame over the data wire an at least three bit operation code, wherein two permutations of the operation code are reserved to provide one of the guaranteed bits in the operation code.

28. A system in accordance with claim 27 , wherein the two-wire interface is a guaranteed header two-wire interface.

29. A system in accordance with claim 27 , wherein the two-wire interface is not a guaranteed header two-wire interface.

30. A system in accordance with claim 27 , wherein the data wire is pulled high when no components are asserting binary values on the data wire.

31. A system in accordance with claim 27 , wherein the data wire is pulled low when no components are asserting binary values on the data wire.

32. A system in accordance with claim 27 , wherein the preamble is automatically asserted on the data wire without the master component or the slave component needing to affirmatively assert the preamble on the data wire.

33. A system in accordance with claim 27 , wherein the number of bits in the non-preamble portions of the frame is at least double the predetermined number “n” of bits in the preamble.

34. A master component that is configured to do the following when coupled to a slave component via a clock wire and a data wire:

determining that an operation is to be performed on the slave component;

monitoring the data wire of the two-wire interface upon determining that the operation is to be performed on the slave component;

detecting at least a predetermined number “n” of consecutive bits of the same binary polarity that have occurred on the data wire while monitoring the data wire, the predetermined number of consecutive bits comprising a preamble of a frame, the number of bits in the non-preamble portions of the frame being at least double the predetermined number “n” of bits in the preamble;

transmitting an at least three bit operational code designating an operation state and a structure of the frame; and

transmitting non-preamble portions of the frame over the data wire with guaranteed bits unconditionally inserted in predetermined bit positions that are positioned at least every “n” consecutive bit positions in the non-preamble portions of the frame, each predetermined bit position being offset a predetermined number of consecutive bit positions from the last bit position of the preamble, the guaranteed bits being opposite in polarity with respect to the preamble bits' polarity.

35. A master component in accordance with claim 34 , wherein the two-wire interface is a guaranteed header two-wire interface.

36. A master component in accordance with claim 34 , wherein the two-wire interface is not a guaranteed header two-wire interface.

37. A master component in accordance with claim 34 , wherein the master component is implemented in a laser transmitter/receiver.

38. A master component in accordance with claim 37 , wherein the laser transmitter/receiver is a 1G laser transceiver, a 2G laser transceiver, a 4G laser transceiver, a 10G laser transceiver, or a laser transceiver suitable for fiber channels greater than 10G.

39. A master component in accordance with claim 37 , wherein the laser transmitter/receiver is an XFP laser transceiver, an SFP laser transceiver, or an SFF laser transceiver.

40. A master component in accordance with claim 34 , wherein the preamble is automatically asserted on the data wire without the master component or the slave component needing to affirmatively assert the preamble on the data wire.

41. A master component in accordance with claim 34 , wherein the master component is further configured to do the following when coupled to a slave component via a clock wire and a data wire: determining, as a direct consequence of detecting the preamble on the data wire, that the slave component is not transmitting over the data wire and that it is safe for the master component to transmit over the data wire.