Read/write separation in video request manager

1. A video request manager comprising:

a first state machine configured to command a memory controller to fetch reference pixels for a first portion of a picture; and

a second state machine configured to command the memory controller to write a second portion of the picture,

wherein in response to a resource contention between the command to fetch the reference pixels for the first portion of the picture and the command to write the second portion of the picture, the memory controller gives priority to the command to fetch the reference pixels for the first portion of the picture over the command to write the second portion of the picture, and

wherein the second state machine loads the memory controller with the second portion of the picture while the memory controller concurrently fetches the reference pixels for the first portion of the picture.

2. The video request manager of claim 1 , wherein the second state machine commands the memory controller to write the second portion to a frame buffer, such that the resource contention occurs between the command to fetch the reference pixels from the frame buffer, and the command to write the second portion to the frame buffer.

3. A circuit for decoding video data, comprising:

a motion vector address computer configured to calculate at least one address for reference pixels for a first portion of a picture;

a motion compensator configured to apply a prediction error from a second portion of the picture to reference pixels fetched for the second portion of the picture;

a video request manager comprising:

a first state machine configured to issue a command to fetch the reference pixels for the first portion of the picture; and

a second state machine configured to issue a command to write the second portion of the picture; and

a memory controller configured to fetch the reference pixels for the first portion after the first state machine issues the command to fetch, and write the second portion of the picture after the second state machine issues the command to write, and

wherein the second portion of the picture is loaded in the memory controller while the memory controller concurrently fetches the reference pixels for the first portion of the picture, and

wherein the motion compensator applies the prediction error from the second portion of the picture to the reference pixels fetched for the second portion of the picture while the motion vector address computer concurrently calculates the at least one address for the reference pixels for the first portion of the picture.

4. The circuit of claim 3 , wherein the memory controller further comprises:

an arbiter for causing the memory controller to give priority to the command to fetch the reference pixels for the first portion of the picture over the command to write the second portion of the picture.

5. The circuit of claim 3 , wherein the memory controller further comprises:

a write buffer for storing the second portion of the picture while concurrently fetching the reference pixels for the first portion of the picture.

6. The circuit of claim 5 , wherein the memory controller is further configured to write the second portion of the picture from the write buffer to a memory system, after fetching the reference pixels for the first portion of the picture.

7. The video request manager of claim 1 , wherein the second state machine loads a buffer of the memory controller with the second portion while the memory controller concurrently fetches the reference pixels for the first portion of the picture.

8. The video request manager of claim 1 , wherein the first portion of the picture is decoded using the reference pixels fetched for the first portion of the picture to generate the decoded first portion of the picture.

9. The circuit of claim 3 , wherein the motion vector address computer is further configured to calculate at least one address for the reference pixels for the second portion of the picture.

10. The circuit of claim 9 , wherein the motion compensator is configured to decode the second portion of the picture using the reference pixels fetched for the second portion of the picture.

11. The circuit of claim 9 , wherein the memory controller is further configured to fetch the reference pixels for the second portion of the picture based upon the at least one address for the reference pixels for the second portion of the picture.

12. The circuit of claim 3 , wherein the memory controller is further configured to fetch the reference pixels for the second portion of the picture after the first state machine issues the command to fetch the reference pixels for the second portion of the picture, and write the first portion of the picture after the second state machine issues the command to write the first portion, and wherein the first portion of the picture is loaded in a write buffer of the memory controller while the memory controller concurrently fetches the reference pixels for the second portion of the picture.

13. The circuit of claim 12 , wherein the memory controller writes the first portion of the picture from the write buffer to a memory system, after fetching the reference pixels for the second portion of the picture.

14. A circuit for decoding video data, comprising:

a video request manager comprising:

a first state machine configured to issue a command to fetch, from a frame buffer, reference pixels for an encoded portion of a picture; and

a second state machine configured to issue a command to write, to the frame buffer, a decoded portion of the picture; and

a memory controller configured to fetch the reference pixels for the encoded portion of the picture in response to the command issued by the first state machine, and write the decoded portion of the picture in response to the command issued by the second state machine,

wherein in response to a resource contention between the command to fetch the reference pixels for the encoded portion of the picture and the command to write the decoded portion of the picture, the memory controller gives priority to the command to fetch the reference pixels for the encoded portion of the picture over the command to write the decoded portion of the picture, and

wherein the decoded portion of the picture is loaded in a write buffer of the memory controller while the memory controller concurrently fetches the reference pixels for the encoded portion of the picture.

15. The circuit of claim 14 , wherein the reference pixels are chroma reference pixels to decode the encoded portion of the picture and the decoded portion of the picture is a decoded luma portion of the picture.

16. The circuit of claim 14 , wherein the reference pixels are luma reference pixels to decode the encoded portion of the picture and the decoded portion of the picture is a decoded chroma portion of the picture.

17. The video request manager of claim 1 , wherein:

the first portion of the picture is a chroma portion of the picture, and

the second portion of the picture is a luma portion of the picture.

18. The video request manager of claim 1 , wherein:

the first portion of the picture is a luma portion of the picture, and

the second portion of the picture is a chroma portion of the picture.

19. The circuit of claim 3 , wherein:

the first portion of the picture is a chroma portion of the picture, and

the second portion of the picture is a luma portion of the picture.

20. The circuit of claim 3 , wherein:

the first portion of the picture is a luma portion of the picture, and

the second portion of the picture is a chroma portion of the picture.