Motion vector address computer error detection
Described herein is a video decoding related system and method for error detection in a motion vector address computer. A circuit determines addresses for reference pixels. The circuit comprises an input and logic. The input receives parameters comprising a picture type indicator for indicating a type of a picture. The logic determines whether the parameters received by the input are valid.
1 . A circuit for determining addresses for reference pixels, said circuit comprising:
an input for receiving parameters, the parameters comprising a picture type indicator for indicating a type of a picture; and
logic for determining whether the parameters received by the input are valid.
2 . The circuit of claim 1 , further comprising:
an arithmetic logic unit for calculating one or more addresses depending on whether the logic determines that the addresses are valid.[IPai_Bkar5]
3 . The circuit of claim 1 , wherein the logic determines whether the parameters received by the input are valid based on the picture type indicator and the number of motion vectors received by the input.
4 . The circuit of claim 3 , further comprising:
a control register for providing the type of pictures and indicating the number of motion vectors received to the logic.
5 . The circuit of claim 4 , further comprising:
one or more motion vector registers for storing motion vectors received by the input; and
wherein the control register comprises one or more bits, each of which are associated with a corresponding one or the one or more motion vector registers, wherein the one or more bits are in a particular state, based on whether the corresponding motion vector register stores a motion vector.
6 . The circuit of claim 5 , wherein the logic determines that the parameters are invalid if the control register indicates that the type of picture is an I-picture and any of the one or more bits are in the particular state.
7 . The circuit of claim 5 , wherein the logic determines that the parameters are invalid if the control register indicates that the type of picture is a B-picture and less than two of the one or more bits are in the particular state.
8 . A method for determining addresses for reference pixels, said method comprising:
receiving parameters, the parameters comprising a picture type indicator for indicating a type of a picture; and
determining the validity of the parameters; and
calculating one or more addresses after determining the validity of the parameters, if the parameters are valid.
9 . The method of claim 8 , further comprising:
fetching pixels from the one or more addresses after determining the validity of the parameters, if the parameters are valid.
10 . The method of claim 8 , wherein determining the validity of the parameters is based on the picture type indicator and the number of motion vectors received.
11 . The method of claim 10 , wherein determining the validity of the parameters further comprises determining that the parameters are invalid if the type of picture is an I-picture and any motion vectors are received.
12 . The method of claim 10 , wherein determining the validity of the parameters further comprises determining that the parameters are invalid if the control register indicates that the type of picture is a B-picture and less than two of the one or more bits are in the particular state.
13 . A video decoder for decoding macroblocks, said video decoder comprising:
a processor for decoding a set of parameters, said set of parameters comprising:
a picture type parameter indicating a type of picture; and
motion vectors indicating reference pixels associated with the macroblock;
a motion vector address computer for determining the validity of the set of parameters, and calculating addresses associated with motion vectors if the set of parameters are valid; and
a video request manager for fetching reference pixels at the addresses calculated by the motion vector address computer, if the motion vector address computer determines that the set of parameters are valid.
14 . The video decoder of claim 13 , wherein the motion vector address computer further comprises:
an input for receiving parameters, the parameters comprising a picture type indicator for indicating a type of a picture; and
logic for determining whether the parameters received by the input are valid.
15 . The video decoder of claim 14 , wherein the motion vector address computer further comprises:
an arithmetic logic unit for calculating one or more addresses after the logic determines that the addresses are valid.
16 . The video decoder of claim 14 , wherein the logic determines whether the parameters received by the input are valid based on the picture type indicator and the number of motion vectors received by the input.
17 . The video decoder of claim 16 , wherein the motion vector address computer further comprises:
a control register for providing the type of pictures and indicating the number of motion vectors received to the logic.
18 . The video decoder of claim 17 , wherein the motion vector address computer further comprises:
one or more motion vector registers for storing motion vectors received by the input; and
wherein the control register comprises one or more bits, each of which are associated with a corresponding one or the one or more motion vector registers, wherein the one or more bits are in a particular state, based on whether the corresponding motion vector register stores a motion vector.
19 . The video decoder of claim 18 , wherein the logic determines that the parameters are invalid if the control register indicates that the type of picture is an I-picture and any of the one or more bits are in the particular state.
20 . The video decoder of claim 18 , wherein the logic determines that the parameters are invalid if the control register indicates that the type of picture is a B-picture and less than two of the one or more bits are in the particular state.