Transconductance control circuit of rail-to-rail differential input stages
View Patent ↗A transconductance control circuit of a rail-to-rail differential input stage is described. The transconductance control circuit senses the gate-source voltages of PMOS and NMOS differential pairs, converts the sensed voltage to a current, compares the current with a reference current, and controls the currents of the PMOS and NMOS differential pairs to control the transconductance of the RTR differential input stage. Also, various types of biasing techniques and matching techniques are used to reduce the variations of the transconductance.
1. A transconductance control circuit of a rail-to-rail differential input stage, comprising:
a rail-to-rail differential input stage including a first and a second differential pair;
a current supply unit coupled to sources of the first and second differential pairs, for supplying a bias current; and
a transconductance controller for respectively sensing a first gate-source voltage of the first differential pair and a second gate-source voltage of the second differential pair, for comparing a reference current with a current that corresponds to sum of the first gate-source voltage and the second gate-source voltage, and for controlling currents of the first and second differential pairs according to the comparison.
2. The transconductance control circuit of claim 1 , wherein
the first and second differential pairs comprise transistors, and
the transistors of the first and second differential pair have different conduction types.
3. The transconductance control circuit of claim 2 , wherein the transistors of the first differential pair are n-type, and the transistors of the second differential pair are p-type.
4. The transconductance control circuit of claim 2 , wherein the transconductance controller comprises:
a gate-source voltage equivalent current sensor for respectively sensing a first gate-source voltage of the first differential pair and a second gate-source voltage of the second differential pair, and for generating a current that corresponds to the sum of the first gate-source voltage and the second gate-source voltage;
a current comparator for comparing the current of the gate-source voltage equivalent current sensor with the reference current; and
a voltage controlled current source for controlling the currents of the first and second differential pairs according to the output of the current comparator.
5. The transconductance control circuit of claim 4 , wherein the gate-source voltage equivalent current sensor comprises:
a first gate-source voltage sensor for sensing the first gate-source voltage of the first differential pair;
a second gate-source voltage sensor for sensing the second gate-source voltage of the second differential pair;
an adder for summing an output of the first gate-source voltage sensor and an output of the second gate-source voltage sensor; and
a current generator for converting a voltage that corresponds to an output of the adder into a current.
6. The transconductance control circuit of claim 5 , wherein the reference current is greater than about eight times the current of a power supply unit.
7. The transconductance control circuit of claim 4 , wherein the gate-source voltage equivalent current sensor comprises:
a first transistor coupled to a source of the second differential pair, for sensing the second gate-source voltage of the second differential pair; and
a second transistor having a gate coupled to a source of the first differential pair, for sensing the gate-source voltage of the first differential pair, wherein
sources of the first and second transistors are coupled with each other to generate a current proportional to the sum of the first gate-source voltage and the second gate-source voltage.
8. The transconductance control circuit of claim 7 , wherein the current comparator comprises:
a third transistor having a gate and a drain coupled to a drain of the first transistor; and
a fourth transistor having a gate coupled to a gate of the third transistor, and a drain coupled to the reference current; and wherein
the current comparator duplicates a current proportional to the sum of the first gate-source voltage and the second gate-source voltage, and compares the current with the reference current.
9. The transconductance control circuit of claim 7 , wherein the voltage controlled current source comprises a fifth transistor having a gate coupled to the drain of the fourth transistor, a drain coupled to the source of the second differential pair, and a source coupled to the source of the first differential pair, wherein
the voltage controlled current source controls the currents of the first and second differential pairs.
10. The transconductance control circuit of claim 9 , wherein the transconductance controller further comprises a reference current generator for generating the reference current.
11. The transconductance control circuit of claim 10 , wherein the reference current generator of the transconductance controller comprises:
a sixth and a seventh transistor, forming a current mirror, having an output end coupled to the gate of the fifth transistor, the current mirror providing the reference current;
an eighth and a ninth transistor, having gates coupled to each other, and sources coupled to a first and a second reference current source respectively, the coupled gates being coupled to a bias voltage;
a tenth transistor, having a gate coupled to the source of the eighth transistor; and
an eleventh transistor, having a gate coupled to the source of the ninth transistor, a source coupled to a source of the tenth transistor, and a drain coupled to the drain of the sixth transistor, the eighth to eleventh transistors supplying the reference current, and the sixth and seventh transistors duplicating the reference current to perform a replica biasing technique.
12. The transconductance control circuit of claim 11 , wherein the bias voltage has a value between a summed value of the gate-source voltage of the first differential pair and an operating voltage of the current supply unit of the first differential pair, and a summed value of the gate-source voltage of the second differential pair and an operating voltage of the current supply unit of the second differential pair.
13. The transconductance control circuit of claim 12 , wherein the fifth transistor is an NMOS transistor.
14. The transconductance control circuit of claim 10 , wherein the reference current generator of the transconductance controller comprises:
a sixth and a seventh transistor, forming a current mirror having an output end coupled to the gate of the fifth transistor, the current mirror providing the reference current;
an eighth and a ninth transistor, having gates coupled to each other and coupled to the sources of the fifth transistors, and having sources respectively coupled to a first and a second reference current source;
a tenth transistor, having a gate coupled to the source of the eighth transistor; and
an eleventh transistor, having a gate coupled to the source of the ninth transistor, a source coupled to a source of the tenth transistor, and a drain coupled to the drain of the sixth transistor, the eighth to eleventh transistors supplying the reference current, and the sixth and seventh transistors duplicating the reference current to perform a dynamic biasing technique.
15. The transconductance control circuit of claim 14 , wherein the transconductance controller further comprises:
a twelfth transistor having a gate and a drain coupled to each other, the drain being coupled to the drain of the tenth transistor, and a source coupled to the current supply unit for producing an essentially matching state between the gate-source voltage equivalent current sensor and the reference current generator; and
a thirteenth transistor having a gate and a drain coupled to each other, the drain being coupled to the drain of the second transistor, and a grounded source for producing an essentially matching state between the gate-source voltage equivalent current sensor and the reference current generator.