Power-mode control circuitry for power converters

1. A power-mode control circuitry for a power converter, comprising: a filter, for converting a switching current into an average-current signal; a voltage divider, for generating an average-voltage signal in response to an input voltage of the power converter; a multiplier, for producing a power signal by multiplying said average-current signal with said avenge-voltage signal; a power-level threshold; and an error amplifier, for generating a programming signal by comparing said power signal with said power-level threshold, wherein said programming signal is utilized to control said switching signal for achieving power-mode control.

2. The power-mode control circuitry of claim 1 , wherein said programming signal is compared with a current-sense signal for controlling said switching signal, wherein said current-sense signal is converted from said switching current, and wherein said switching current is adjusted to accomplish a constant power output.

3. The power-mode control circuitry of claim 1 , wherein said power-level threshold is generated in proportion to an output voltage of the power converter, wherein said programming signal is compared with said current-sense signal to control said switching signal, and wherein said switching current is adjusted to accomplish a constant current output.

4. The power-mode control circuitry of claim 1 , wherein said power-level threshold is generated in proportion to said output voltage of the power converter, wherein said programming signal is applied to control a switching frequency of said switching signal, and wherein the switching frequency of said switching signal is adjusted to accomplish a constant current output.

5. The power-mode control circuitry of claim 1 , wherein said multiplier comprises: a timing generator, for generating a first timing signal and a second timing signal in response to a pulse signal, wherein said pulse signal is generated by an oscillator of a PWM controller of the power converter; a charge-control circuit, formed by a current source, a first capacitor and a comparator, wherein said average-voltage signal is supplied to a positive input of said comparator, wherein said first capacitor is connected between a negative input of said comparator and a ground reference, and wherein said first capacitor is charged by said current source; a V-to-I circuit, formed by an operational amplifier, a first resistor, a first transistor, wherein said V-to-I circuit generates a first current in response to said average-current signal; a current mirror, formed by a first-mirror transistor and a second-mirror transistor, wherein said current mirror generates a mirror current from said first current; a second capacitor, charged by said mirror current, for generating a multiplied voltage; an on/off transistor, controlled by said charge-control circuit for switching on/off said mirror current, wherein an output of said comparator controls a gate of said on/off transistor; a drain of said on/off transistor is driven by said mirror current, and a source of said on/off transistor is connected to said second capacitor, a first switch, controlled by said second timing signal, for discharging said first capacitor; a second switch, controlled by said second timing signal, for discharging said second capacitor; an output capacitor, for holding an output voltage of said multiplier, wherein said average-current signal multiplies with said average-voltage signal to generate said output voltage of said multiplier; an output switch, controlled by said first timing signal to switch said multiplied voltage to said output capacitor, wherein said output switch is connected between said second capacitor and said output capacitor.

6. The power-mode control circuitry of claim 3 , further comprising: a sampling amplifier, for receiving a sampled voltage and generating a sample-feedback signal in response to the output voltage of the power converter, wherein said sampled voltage containing output voltage information is used for generating said power-level threshold, and wherein said sample-feedback signal is applied for feedback loop control.