Storing results of producer instructions to facilitate consumer instruction dependency tracking
View Patent ↗If a consumer instruction specifies a 64 bit source register comprised of results provided by two 32 bit producer instructions, the number of dependencies that must be tracked per source register can be decreased by transforming one or more of the 32 bit producer instructions so that rather than simply storing its result in a 32 bit destination register, the transformed instruction stores its result into a 64 bit logical register along with another 32 bit value held in another 32 bit register.
1. A method facilitating dependency tracking by a processor that overlays plural lesser-width logical registers on each of at least some greater-width logical registers, the method comprising:
generating an efficiency predictor, wherein said generating step includes selectively asserting a signal based on a processor performance metric by determining a number of pipeline stalls and comparing the number of pipeline stalls to a threshold value; and
based on the efficiency predictor, placing a lesser-width instruction result destined for a first lesser-width logical register into either the first lesser-width local register or a greater-width logical register along with one or more lesser-width values held in other lesser-width logical registers.
2. A method facilitating dependency tracking by a processor that overlays plural lesser-width logical registers on each of at least some greater-width logical registers, the method comprising:
generating an efficiency predictor, wherein said generating step includes selectively asserting a signal based on a processor performance metric by determining a number of times the placing has been performed and comparing the number of times the placing has been performed to a threshold value; and
based on the efficiency predictor, placing a lesser-width instruction result destined for a first lesser-width logical register into either the first lesser-width local register or a greater-width logical register along with one or more lesser-width values held in other lesser-width logical registers.
3. A method for use in a processor, the method comprising:
selecting, in an execution sequence of instructions, an original instruction configured to produce a lesser-width result and place the result into a first lesser-width logical register, based on a processor performance metric, an age counter or an efficiency predictor;
said selecting step includes determining a number of pipeline stalls and comparing the number of pipeline stalls to a threshold value; and
transforming the original instruction into a transformed instruction configured to place the result of the original instruction into a greater-width logical register along with one or more lesser-width values held in other lesser-width logical registers.
4. A processor comprising:
one or more execution units;
a plurality of greater-width registers capable of accommodating aliased lesser-width registers, the plurality of greater width registers coupled to said one or more execution units;
a decode unit coupled to said plurality of greater width registers and said one or more execution units, said decode unit, in response to an efficiency predictor, is operable to modify an original instruction specifying a first lesser-width register as a destination register, the modified instruction loading a result of the original instruction and a value held in a second lesser-width register into a single greater width register; and
wherein the decode unit includes at least one counter, and wherein the decode unit modifies the original instruction based on a value of the at least one counter.
5. The processor as in claim 4 wherein the at least one counter is to indicate a number of pipeline stalls.
6. The processor as in claim 4 wherein the at least one counter is to indicate a period during which instructions have been modified.
7. A processor that selectively modifies an instruction sequence presented thereto for execution, the selective modification replacing an original instruction of the instruction sequence to generate a modified instruction, wherein the original instruction specifies a first lesser-width register as a destination register, and the modified instruction specifies loading a result of the original instruction and a value held in a second lesser-width register into a single greater width register, comprising:
at least one counter, wherein the processor selectively modifies the instruction sequence based on a value of the at least one counter; and
the processor placing the result of the original instruction and the value held in the second lesser-width register into the single greater width register.
8. The processor as in claim 7 wherein the at least one counter is to indicate a number of pipeline stalls.
9. The processor as in claim 7 wherein the at least one counter is to indicate a period during which instructions have been modified.
10. A processor comprising:
means for controlling under what circumstances an original instruction, specifying a first lesser-width register as a destination register, is permitted to be modified, said means for controlling includes means for initiating modification of the original instruction to occur based on a performance metric;
means for modifying, the original instruction when said means for controlling permits; and
means for loading a result of the original instruction and a value held in a second lesser-width register into a single greater-width register in response to the modified instruction, said second lesser-width register not within the greater-width register.
11. The processor as in claim 10 wherein the control means further includes means for determining a number of pipeline stalls.
12. The processor as in claim 10 wherein the control means further includes means for determining a period during which instructions have been modified.