IP Library Granted Patent US 6,985,030
Granted Patent B2
US 6,985,030 · App. 10/818,791 · Granted Jan 10, 2006

Differential amplifier, two-stage amplifier including the differential amplifier, and analog-to-digital converter including the differential amplifier

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Quick Facts
Patent No.
US 6,985,030
App. No.
10/818,791
Granted
Jan 10, 2006
Kind
B2
Abstract

A differential amplifier has an in-phase input terminal to which an input signal is applied through a first switching unit, an anti-phase input terminal to which a reference signal is applied through a second switching unit, and a third switching unit between the in-phase and anti-phase input terminals. The potential difference between the in-phase and anti-phase input terminals is differentially amplified by setting the first and second switching units to be on and the third switching unit to be off. Also, the in-phase and anti-phase input terminals are short-circuited to have a high impedance by setting the first and second switching units to be off and the third switching unit to be on.

Claims (21)

1. A two-stage amplifier having an offset-compressing function, comprising a prestage differential amplifier and a poststage differential amplifier, the prestage and poststage differential amplifiers being connected in series to each other,

wherein:

the offset-compressing function compresses an offset voltage of said prestage differential amplifier by increasing the gain of said poststage differential amplifier;

the prestage differential amplifier has thereon an in-phase input terminal and an anti-phase input terminal,

the prestage amplifier comprises:

a first switching unit provided on an input signal line connected to the in-phase input terminal,

a second switching unit provided on a reference signal line connected to the anti-phase input terminal, and

a third switching unit provided between the in-phase input terminal and the anti-phase input terminal;

a difference in potential between the in-phase input terminal and the anti-phase input terminal is differentially amplified by setting said first switching unit and said second switching unit to be on and said third switching unit to be off; and

the in-phase input terminal and the anti-phase input terminal are short-circuited to have a high impedance by setting said first switching unit and said second switching unit to be off and said third switching unit to be on.

2. An analog-to-digital converter comprising a plurality of amplifying means,

wherein:

an input signal is converted into digital form by amplifying differences between an input signal and each of a plurality of different reference signals;

each of said plurality of amplifying means is a two-stage amplifier comprising a prestage differential amplifier and a poststage differential amplifier which are connected in series to each other, and having an offset-compressing function for compressing an offset voltage of said prestage differential amplifier by increasing the gain of said poststage differential amplifier;

each prestage differential amplifier has thereon an in-phase input terminal and an anti-phase input terminal;

each prestage amplifier comprises:

a first switching unit provided on an input signal line connected to the in-phase input terminal,

a second switching unit provided on a reference signal line connected to the anti-phase input terminal, and

a third switching unit provided between the in-phase input terminal and the anti-phase input terminal:

a difference in potential between the in-phase input terminal and the anti-phase input terminal is differentially amplified by setting said first switching unit and said second switching unit to be on and said third switching unit to be off; and

the in-phase input terminal and the anti-phase input terminal are short-circuited to have a high impedance by setting said first switching unit and said second switching unit to be off and said third switching unit to be on.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040419/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2004
From: SHIMIZU, YASUHIDE; HIDEYUKI, KATSUTA; YAMASITA, YUKITOSI; YOKOYAMA, NOBUHIKO
To: SONY CORPORATION
Reel/Frame 015192/0807 →