High linearity, high efficiency power amplifier with DSP assisted linearity optimization

1. A method for calibrating a power amplifier that services a communications transceiver, the method comprising:

producing a test signal to test the power amplifier, wherein the power amplifier has a primary transconductance stage, a secondary transconductance stage, a cascode stage and an inductive load, in which a primary bias setting is coupled to the primary transconductance stage and a secondary bias setting is coupled to the secondary transconductance stage;

applying the test signal to calibrate the bias settings by:

(i) applying a first bias voltage to a gate of a metal oxide silicon transistor of the cascode stage and applying a second bias voltage to a base of a parasitic bipolar transistor formed in parallel with the metal oxide silicon transistor;

(ii) applying a respective bias setting to the primary and secondary transconductance stages of the power amplifier;

(iii) applying the test signal to the power amplifier to produce an amplified test signal;

(iv) coupling back a portion of the amplified test signal to a receiver section of the communications transceiver;

(v) producing a characterization of the amplified test signal, wherein the characterization indicates at least one of an error vector magnitude, intermodulation product magnitude, or 1 dB compression point of the amplified test signal;

(vi) repeating (i) through (v) for respective set of bias settings, until a plurality of bias settings have been tested; and

determining power amplifier bias control settings to operate the power amplifier, based upon the plurality of characterizations of the amplified test signal and the respective set of bias settings, so that the power amplifier has its response linearized to minimize error vector magnitude and intermodulation product magnitude; and

applying the power amplifier bias control settings to the power amplifier.

2. The method of claim 1 , wherein the power amplifier bias control settings are determined during at least one of start up, reset, and idle periods of the communications transceiver.

3. The method of claim 1 , wherein the power amplifier bias control settings include at least one of a minimum bias setting and a maximum bias setting.

4. The method of claim 1 , wherein the power amplifier bias control settings include a relationship between input signal level and applied bias level.

5. The method of claim 1 , wherein the power amplifier bias control settings include a minimum bias setting, a maximum bias setting, and a relationship between input signal level and applied bias level.

6. The method of claim 1 , wherein in some operations the metal oxide silicon transistor is turned off by a particular setting of the first bias voltage.

7. The method of claim 1 , wherein in some operations the parasitic bipolar transistor is turned off by a particular setting of the second bias voltage.

8. The method of claim 1 , wherein in some operations the metal oxide silicon transistor is turned on by the first bias voltage and the parasitic bipolar transistor is turned on by the second bias voltage.

9. A communications transceiver comprising:

a baseband processor;

a receiver section coupled to the baseband processor;

a transmitter section coupled to the baseband processor that includes a power amplifier, wherein the power amplifier has a primary transconductance stage, a secondary transconductance stage, a cascode stage and an inductive load, in which a primary bias setting is coupled to the primary transconductance stage and a secondary bias setting is coupled to the secondary transconductance stage; and

wherein in a calibration operation:

(i) the baseband processor produces a test signal to the transmitter section;

(ii) the baseband processor causes a first bias voltage to be applied to a gate of a metal oxide silicon transistor of the cascode stage and a second bias voltage to be applied to a base of a parasitic bipolar transistor formed in parallel with the metal oxide silicon transistor;

(iii) the baseband processor causes a respective bias setting to be applied to the primary and secondary transconductance stages of the power amplifier:

(iv) for the respective bias setting, the power amplifier produces an amplified test signal;

(v) for the respective bias setting, the receiver section couples back a portion of the amplified test signal to the baseband processor;

(vi) for the respective bias setting, the baseband processor produces a characterization of the amplified test signal, wherein the characterization indicates at least one of an error vector magnitude, intermodulation product magnitude, or 1 dB compression point of the amplified test signal;

(vii) the baseband processor repeats (ii) through (v) for respective set of bias settings, until a plurality of bias settings have been tested; and

(viii) the baseband processor, based upon a plurality of characterizations of the amplified test signal and the respective set of power amplifier bias settings, determines power amplifier bias control settings, so that the power amplifier has its response linearized to minimize error vector magnitude and intermodulation product magnitude; and

the baseband processor to apply the power amplifier bias control settings to the power amplifier.

10. The communications transceiver of claim 9 , wherein the power amplifier bias control settings are determined during at least one of start up, reset, and idle periods of the communications transceiver.

11. The communications transceiver of claim 9 , wherein the power amplifier bias control settings include at least one of a minimum bias setting and a maximum bias setting.

12. The communications transceiver of claim 9 , wherein the power amplifier bias control settings include a relationship between input signal level and applied bias level.

13. The communications transceiver of claim 9 , wherein the power amplifier bias control settings include a minimum bias setting, a maximum bias setting, and a relationship between input signal level and applied bias level.

14. The communications transceiver of claim 9 , wherein in some operations the metal oxide silicon transistor is turned off by a particular setting of the first bias voltage.

15. The communications transceiver of claim 9 , wherein in some operations the parasitic bipolar transistor is turned off by a particular setting of the second bias voltage.

16. The communications transceiver of claim 9 , wherein in some operations the metal oxide silicon transistor is turned on by the first bias voltage and the parasitic bipolar transistor is turned on by the second bias voltage.

17. The communications transceiver of claim 9 , further comprising a baseband signal generator that produces the test signal.

18. The communications transceiver of claim 9 , wherein the test signal is representative of a modulated signal to be produced by the communications transceiver during normal operations.