Single chip multi-antenna wireless data processor

1. A radio frequency (RF) multi-antenna access point system implemented in a single chip integrated circuit chip (IC) comprising:

a baseband processor circuit located in a first portion of the single chip IC, the baseband processor circuit to handle data transmissions during a first operating mode in a channel between a first access point and a second access point; and

a multi-antenna signal processing circuit located in an Application Specific Integrated Circuit (ASIC) in a second portion of the single chip IC, the multi-antenna signal processing circuit to handle data transmissions during a second operating mode in said channel, said multi-antenna signal processing circuit being further:

(a) configured to receive M independent RF modulated input signals from said second access point; and

(b) configured to process said M independent RF modulated input signals using a channel mixing matrix and estimated channel coefficients b 1 , b 2 to extract N independent data signals transmitted by said second access point;

wherein said first operating mode and said second operating mode are to be automatically selected by the RF multi-antenna access point system based on a transmission condition in said channel.

2. The RF multi-antenna access point system of claim 1 , wherein said multi-antenna signal processing circuit includes an analog to digital converter, and a digital to analog converter for interfacing to an antenna.

3. The RF multi-antenna access point system of claim 2 , wherein said multi-antenna signal processing circuit includes a Fast Fourier Transform (FFT) Circuit.

4. The RF multi-antenna access point system of claim 3 , wherein said multi-antenna signal processing circuit includes a preamble acquisition circuit for performing a preamble acquisition to align an FFT data frame with an 802.11 x based data stream.

5. The RF multi-antenna access point system of claim 1 , wherein said multi-antenna signal processing circuit is to process at least 4 separate input signals representing a data stream multiplexed over 4 separate bit streams.

6. The RF multi-antenna access point system of claim 1 , wherein said channel mixing matrix is to compute a recovered data signal x as follows:

x=b 1* y 1+ b 2* y 2+ x 0,

where the b 1 and the b 2 are channel equalization coefficients to be computed by said multi-antenna signal processing circuit, y 1 and y 2 are received data from separate baseband channels, and x 0 is a recovered signal from an adjacent ASIC internal to the single chip IC.

7. The RF multi-antenna access point system of claim 1 , wherein space division multiple access is to be realized by separating different RF signals from different directions simultaneously in the single chip IC.

8. The RF multi-antenna access point system of claim 1 , wherein said multi-antenna signal processing circuit is to extend a data transmission range that can be achieved by said baseband processor circuit between said first access point and said second access point.

9. The RF multi-antenna access point system of claim 1 , wherein said multi-antenna signal processing circuit is to increase a data transmission rate that can be achieved by said baseband processor circuit between said first access point and said second access point.

10. The RF multi-antenna access point system of claim 1 , wherein said multi-antenna signal processing circuit is to transmit M separate data signals to said second access point.

11. The RF multi-antenna access point system of claim 10 , wherein a localized encryption is to be achieved for said second access point by independently controlling said M separate transmission signals.

12. The RF multi-antenna access point system of claim 1 , wherein said first access point can be configured during a data transmission to transmit with an energy level which is substantially the same as a noise level to locations other than a localized region where said second access point is located.

13. An 802.11x compatible radio frequency (RF) multi-antenna access point enhancement circuit implemented in a single chip integrated circuit (IC) comprising:

a multi-antenna signal processing circuit situated in a first portion of the single chip IC and configured as a first access point:

(a) configured to operate simultaneously with a first baseband processor situated in a second portion of the single chip IC, so that said first baseband processor handles data transmissions in a first mode between said first access point, in accordance with an 802.11x protocol, and a second access point under a first channel transmission condition, and said multi-antenna signal processor handles data transmissions in a second mode between said first access point and said second access point in accordance with an 802.11x protocol under a second channel transmission condition;

(b) configured to receive M independent RF modulated input signals from said second access point when the second channel transmission mode exists between the first access point and said second access point;

(c) configured to process said M independent RF modulated input signals using a channel mixing matrix and estimated channel coefficients b 1 , b 2 to extract N independent data signals transmitted by said second access point; and

(d) configured to transmit an RF modulated signal to said second access point using a point coordination function (PCF) mode associated with said 802.11x protocol so as to maintain timing compatibility; and

wherein said multi-antenna signal processing circuit operates with a first baseband processor to receive and transmit RF signals in a channel between said first access point and said second access point.

14. The circuit of claim 13 , wherein said multi-antenna signal processing circuit is to process data using a high rate direct sequence spread spectrum (HR/DSSS) physical layer frame structure that has a preamble and header compatible with said 802.11x protocol.

15. The circuit of claim 13 , wherein said header includes additional data to identify a high rate mode.

16. The circuit of claim 13 , wherein said header includes additional data to identify a modulation format.

17. The circuit of claim 13 , wherein said first baseband processor is to send multicast transmissions to a first set of targets within a first range of said first access point, and said multi-antenna signal processing circuit is to send multicast transmissions to a second set of targets within a second range of said first access point.

18. The circuit of claim 13 , wherein first baseband processor is to communicate with a first set of targets during a first access period, and said multi-antenna signal processing circuit is to communicate with a second set of targets during a second access period.

19. The circuit of claim 18 , wherein said first access period and said second access period are to be alternated at a predetermined ratio.

20. The circuit of claim 13 , wherein said multi-antenna signal processing circuit is to use a wave beam transmission to communicate selectively to a target in a specific location and not to other targets.

21. The circuit of claim 13 , wherein said multi-antenna signal processing circuit is incorporated as part of a closed circuit television monitoring system, and said M independent signals are to be transmitted by N individual cameras.

22. The circuit of claim 13 , wherein a receive sensitivity of said first access point is to be improved by selectively adding additional multi-antenna signal processing circuit modules for a data transmission and/or increasing M.

23. A single chip integrated circuit (IC) radio frequency (RF) multi-antenna access point circuit comprising:

a baseband processor circuit in the single chip IC to handle data transmissions during a first operating mode in a channel between a first access point and a second access point;

a multi-antenna signal processing circuit in the single chip IC to handle data transmissions during a second operating mode in said channel, said multi-antenna signal processing circuit being further:

(a) configured to receive M independent RF modulated input signals from said second access point;

(b) configured to process said M independent RF modulated input signals using a channel mixing matrix and estimated channel coefficients b 1 , b 2 to extract N independent data signals transmitted by said second access point, wherein said first operating mode and said second operating mode are to be automatically selected by the RF multi-antenna access point system based on a transmission condition in said channel;

a modulator/demodulator circuit in the single chip IC to be coupled to an antenna assembly and said multi-antenna signal processing circuit and baseband processor circuit to extract I/Q data samples from an RF modulated received signal;

a media access controller in the single chip IC coupled to said multi-antenna signal processing circuit and baseband processor circuit to interface to a host computing system.

24. A system in a single chip integrated circuit (IC) chip comprising:

a baseband processor circuit located in a first portion of the IC and capable of handling data transmissions during a first operating mode; and

a multi-antenna signal processing circuit located in a second portion of the single chip IC and capable of handling data transmissions during a second operating mode configured to use a channel mixing matrix and estimated channel coefficients b 1 , b 2 to extract N independent data signals transmitted by a second access point,

wherein the multi-antenna signal processing circuit is not utilized during the first operating mode.

25. A system in an IC according to claim 24 , wherein the multi-antenna signal processing circuit is capable of processing M independent modulated input signals using a channel mixing matrix to extract N independent data signals transmitted by an access point.

26. A system in an IC according to claim 24 , wherein the first operating mode and the second operating mode are to be selected by the multi-antenna signal processing circuit based at least on a transmission condition in the channel.

27. A system in an IC according to claim 24 , wherein the multi-antenna signal processing circuit comprises an analog to digital converter or a digital to analog converter, or combinations thereof, being capable of interfacing to an antenna.

28. A system in an IC according to claim 24 , wherein the multi-antenna signal processing circuit comprises a Fast Fourier Transform (FFT) Circuit.

29. A system in an IC according to claim 28 , wherein the multi-antenna signal processing circuit comprises a preamble acquisition circuit capable of performing a preamble acquisition to align an FFT data frame with an IEEE 802.11x type based data stream.

30. A system in an IC according to claim 24 , wherein the multi-antenna signal processing circuit is capable of processing at least 4 separate input signals representing a data stream multiplexed over 4 separate bit streams.

31. A system in a single chip IC according to claim 24 , wherein the multi-antenna signal processing circuit is capable of computing a recovered data signal x as follows:

x=b 1* y 1+ b 2* y 2+ x 0,

where b 1 and b 2 are channel equalization coefficients to be computed by the multi-antenna signal processing circuit, y 1 and y 2 are received data from separate baseband channels, and x 0 is a recovered signal from an adjacent Application Specific Integrated Circuit.

32. A system in an IC according to claim 24 , wherein space division multiple access is to be realized by separating signals from different directions simultaneously or nearly simultaneously in the IC.

33. A system in an IC according to claim 24 , wherein the multi-antenna signal processing circuit is capable of extending a data transmission range that can be achieved by the baseband processor circuit between a first access point and a second access point.

34. A system in an IC according to claim 24 , wherein the multi-antenna signal processing circuit is to increase a data transmission rate that can be achieved by the baseband processor circuit between a first access point and a second access point.

35. A system in an IC according to claim 24 , wherein the multi-antenna signal processing circuit is capable of transmitting M separate data signals to an access point.

36. A system in an IC according to claim 35 , wherein a localized encryption is capable of being achieved for the access point by independently controlling the M separate transmission signals.

37. A system in an IC according to claim 24 , wherein an access point incorporating said IC is capable of being configured during a data transmission to transmit with an energy level which is substantially the same as a noise level to locations other than a localized region to which the data transmission is directed.

38. A system in an IC according to claim 24 , wherein the multi-antenna signal processing circuit is compatible with an IEEE 802.11x type standard.

39. A system in an IC according to claim 24 , wherein the multi-antenna signal processing circuit is capable of operating simultaneously with the first baseband processor and wherein the first baseband processor is capable of handling data transmissions in a first mode between the first access point and a second access point under a first channel transmission condition.

40. A system in an IC according to claim 39 , wherein the multi-antenna signal processing circuit is capable of handling data transmissions in the second mode between a first access point and a second access point in accordance with an IEEE 802.11x type protocol under the second channel transmission condition.

41. A system in an IC according to claim 40 , wherein the multi-antenna signal processing circuit is capable of receiving M independent modulated input signals from the second access point when the second channel transmission mode exists between the first access point and the second access point.

42. A system in an IC according to claim 40 , wherein the multi-antenna signal processing circuit is capable of transmitting modulated signals to the second access point using a point coordination function (PCF) mode associated with the 802.11x type protocol.

43. A system in an IC according to claim 24 , wherein the multi-antenna signal processing circuit is capable of operating with the first baseband processor to receive and transmit signals in a channel between a first access point and a second access point.

44. An integrated circuit (IC) comprising:

a baseband processor circuit capable of handling data transmissions during a first operating mode in a channel between a first access point and a second access point; and

a multi-antenna signal processing circuit capable of handling data transmission during a second operating mode in the channel and configured to use a channel mixing matrix and estimated channel coefficients b 1 , b 2 to extract N independent data signals transmitted by a second access point,

wherein the multi-antenna signal processing circuit is not utilized during the first operating mode.

45. An IC according to claim 44 , further comprising:

a modulator/demodulator circuit to be coupled to an antenna assembly and the multi-antenna signal processing circuit and baseband processor circuit; and

a media access controller coupled to the multi-antenna signal processing circuit and baseband processor circuit and capable of interfacing to a host computing system.