Systems and methods providing ASICs for use in multiple applications

1. A system comprising:

an application specific integrated circuit (ASIC) comprising:

a plurality of components for providing a first level of signal channel reduction and a second level of signal channel reduction, wherein said first and second levels of signal channel reduction are achieved by selecting which of said components to enable; and

a plurality of multiplexers providing N to M signal multiplexing,

wherein in the first level of signal channel reduction said ASIC is configured to provide N to M signal multiplexing;

wherein in the second level of signal channel reduction said ASIC is configured to provide N to M/2 signal multiplexing;

wherein said plurality of multiplexers include N signal inputs, M signal outputs, at least one select signal input, and at least one enable signal input, said enable signal input being utilized in providing said N to M/2 signal multiplexing in said second level of signal channel reduction; and

wherein said plurality of multiplexers are divided into hardwired pairs, and only one of each pair is enabled during a receive operation.

2. The system of claim 1 , wherein at least one of said select signal input and said enable signal input comprise a digital serial control bus.

3. The system of claim 1 , wherein said ASIC comprises:

a circuit configurable to provide a cross-point switch function in the first level of signal channel reduction and to provide a signal summer function in the second level of signal channel reduction.

4. The system of claim 3 , wherein said cross-point switch function comprises selectively routing signal channels to one or more beam formers.

5. The system of claim 3 , wherein the signal summer function comprises a symmetric signal summing operation.

6. The system of claim 5 , wherein the symmetric signal summing operation comprises summing one or more signals that are determined to be of similar weight and delay.

7. A method for using an ASIC that provides a first level of signal channel reduction and a second level of signal channel reduction, the method comprising:

determining a number of signal channels for use in a data path;

configuring the ASIC to provide the determined number of signal channels by selecting one or more components in the ASIC to provide the first or second level of signal channel reduction; and

summing data on each of at least two channels by the ASIC, wherein summing data comprises: receiving signals from a control circuit instructing that certain of the channels are to be divided into symmetric pairs and those pairs added, thereby decreasing the number of output channels; and routing the added pairs to one or more beam formers.

8. The method of claim 7 further comprising operating circuitry on the ASIC as a plurality of multiplexers, thereby decreasing the number of channels from a transducer array to a beam former.

9. The method of claim 8 , wherein the multiplexers are 2:1 multiplexers, and wherein operating as a plurality of multiplexers comprises selectively enabling one of every two 2:1 multiplexers, thereby providing 4:1 multiplexing functionality.

10. The method of claim 9 , wherein selectively enabling comprises stimulating an enable switch on one of every two 2:1 multiplexers by a control signal from a beam former.

11. The method of claim 7 further comprising:

implementing in a sonogram imaging system the ASIC, the one or more beam formers, the data path, and a transducer array, wherein the ASIC, the one or more beam formers, and the transducer array are in communication with the data path.

12. A method for using an ASIC that provides a first level of signal channel reduction and a second level of signal channel reduction, the method comprising:

determining a number of signal channels for use in a data path;

configuring the ASIC to provide the determined number of signal channels by selecting one or more components in the ASIC to provide the first or second level of signal channel reduction; and

summing data on each of at least two channels by the ASIC, wherein summing data comprises: receiving signals from a control circuit instructing that certain of the channels are to be divided into adjacent pairs and those pairs added, thereby decreasing the number of output channels; and routing the added pairs to one or more beam formers.

13. The method of claim 12 further comprising:

implementing in a sonogram imaging system the ASIC, the one or more beam formers, the data path, and a transducer array, wherein the ASIC, the one or more beam formers, and the transducer array are in communication with the data path.

14. The method of claim 12 further comprising:

operating circuitry on the ASIC as a plurality of multiplexers, thereby decreasing the number of channels from a transducer array to the one or more beam formers.

15. The method of claim 14 , wherein the multiplexers are 2:1 multiplexers, and wherein operating as a plurality of multiplexers comprises selectively enabling one of every two 2:1 multiplexers, thereby providing 4:1 multiplexing functionality.

16. The method of claim 15 , wherein selectively enabling comprises stimulating an enable switch on one of every two 2:1 multiplexers by a control signal from the one or more beam formers.

17. A method for using an ASIC that provides a first level of signal channel reduction and a second level of signal channel reduction, the method comprising:

determining a number of signal channels for use in a data path;

configuring the ASIC to provide the determined number of signal channels by selecting one or more components in the ASIC to provide the first or second level of signal channel reduction;

implementing two beam formers in communication with the data path; and

operating the two beam formers and a transducer array to form multiple receive beams.

18. The method of claim 17 further comprising operating the two beam formers and the transducer array perform a multi-line receive operation.

19. A method for using an ASIC that provides a first level of signal channel reduction and a second level of signal channel reduction, the method comprising:

determining a number of signal channels for use in a data path;

configuring the ASIC to provide the determined number of signal channels by selecting one or more components in the ASIC to provide the first or second level of signal channel reduction;

implementing a signal processing unit to communicate with the data path at a number of points;

programming the signal processing unit with code to provide a mode of functionality not originally included in a platform using the method; and

operating the signal processing unit to intercept and insert data along the number of points on the path, thereby instructing the platform to perform the mode.