Integrated transceiver circuit with low interference production and sensitivity
View Patent ↗An integrated transceiver circuit has a reception path, which in turn has a mixer unit for demodulation of a received signal. An analog/digital converter unit is connected in the reception path downstream from the mixer unit. A first frequency divider is connected between the mixer unit and a voltage controlled oscillator in order to predetermine the demodulation frequency. A second frequency divider is connected between the oscillator and the analog/digital converter unit in order to predetermine the sampling frequency.
1. An integrated transceiver circuit, comprising:
a reception path comprising:
a mixer unit configured to demodulate a received signal;
an analog/digital converter unit connected downstream from the mixer unit;
a first voltage controlled oscillator;
a first frequency divider connected between the first voltage controlled oscillator and the mixer unit, and configured to obtain a demodulation frequency for use by the mixer unit; and
a second frequency divider connected between the first voltage controlled oscillator and the analog/digital converter unit, and configured to obtain a sampling frequency for use by the analog/digital converter unit; and
a transmission rath comprising:
a modulator configured to modulate a signal to be transmitted;
a second voltage controlled oscillator;
a third frequency divider connected between the second voltage controlled oscillator and the modulator, and configured to obtain a modulation frequency for use by the modulator;
a digital/analog converter unit connected upstream of the modulator; and
a fourth frequency divider connected between the second voltage controlled oscillator and the digital/analog converter unit, and configured to obtain a sampling frequency for use by the digital/analog converter unit.
2. The integrated transceiver circuit of claim 1 , including a reference frequency input for receiving an external reference frequency, and a first phase locked loop connected between the reference frequency input and the first voltage controlled oscillator.
3. The integrated transceiver circuit of claim 2 , including a second phase locked loop connected between the reference frequency input and the second voltage controlled oscillator.
4. The integrated transceiver circuit of claim 3 , wherein the reception path includes a digital signal processing unit connected downstream from the analog/digital converter unit, the digital signal processing unit having an output which forms a digital output of the reception path.
5. The integrated transceiver circuit of claim 4 , wherein the reception path includes a digital/analog converter unit coupled to the output of the digital signal processing unit, the digital/analog converter unit having an output which forms an analog output of the reception path.
6. The integrated transceiver circuit of claim 4 , wherein the reception path includes a digital signal processing unit connected downstream from the analog/digital converter unit, the digital signal processing unit having an output which forms a digital output of the reception path.
7. The integrated transceiver circuit of claim 6 , wherein the reception path includes a digital/analog converter unit coupled to the output of the digital signal processing unit, the digital/analog converter unit having an output which forms an analog output of the reception path.
8. The integrated transceiver circuit of claim 1 , wherein the reception path includes a digital signal processing unit connected downstream from the analog/digital converter unit, the digital signal processing unit having an output which forms a digital output of the reception path.
9. The integrated transceiver circuit of claim 8 , wherein the reception path includes a digital/analog converter unit coupled to the output of the digital signal processing unit, the digital/analog converter unit having an output which forms an analog output of the reception path.
10. The integrated transceiver circuit of claim 1 , including a reference frequency input for receiving an external reference frequency, and a phase locked loop connected between the reference frequency input and the second voltage controlled oscillator.
11. The integrated transceiver circuit of claim 1 , wherein the transmission path includes a low-pass filter unit connected between the digital/analog converter unit and the modulator.
12. The integrated transceiver circuit of claim 1 , wherein the reception path includes a digital signal processing unit connected downstream from the analog/digital converter unit, the digital signal processing unit having an output which forms an digital output of the reception path.
13. The integrated transceiver circuit of claim 12 , wherein the reception path includes a digital/analog converter unit coupled to the output of the digital signal processing unit, the digital/analog converter unit having an output which forms an analog output of the reception path.
14. The integrated transceiver circuit of claim 1 , including a reference frequency input for receiving an external reference frequency, and a phase locked loop connected between the reference frequency input and the second voltage controlled oscillator.
15. The integrated transceiver circuit of claim 14 , including a further phase locked loop connected between the reference frequency input and the first voltage controlled oscillator.
16. The integrated transceiver circuit of claim 1 , including a reference frequency input for receiving an external reference frequency, and a phase locked loop connected between the reference frequency input and the first voltage controlled oscillator.
17. The integrated transceiver circuit of claim 1 , wherein the modulator is an IQ modulator.
18. The integrated transceiver circuit of claim 1 , wherein the analog/digital converter unit includes first and second analog/digital converters having respective sampling control inputs which are connected to an output of the second frequency divider.
19. The integrated transceiver circuit of claim 1 , wherein the reception path includes a low-pass filter unit connected between the mixer unit and the analog/digital converter unit.
20. The integrated transceiver circuit of claim 1 , wherein the mixer unit is an IQ mixer.
21. The integrated transceiver circuit of claim 1 , wherein the first and second frequency dividers are integer dividers.
22. A method for processing a signal, comprising:
obtaining a demodulation frequency for use by a mixer unit in a reception path of an integrated transceiver circuit with a first frequency divider connected between a first voltage controlled oscillator and the mixer unit;
demodulating a received signal with the mixer unit and the obtained demodulation frequency;
obtaining a sampling frequency for use by an analog to digital converter unit with a second frequency divider connected between the first voltage controlled oscillator and the analog to digital converter unit;
performing a digitizing operation on the demodulated received signal with the analog to digital converter and the obtained sampling frequency;
obtaining a modulation frequency for use by a modulator in a transmission path of the integrated transceiver circuit with a third frequency divider connected between a second voltage controlled oscillator and the modulator;
modulating a signal to be transmitted with the modulator and the obtained modulation frequency;
obtaining a sampling frequency for use by a digital to analog converter unit with a fourth frequency divider connected between the second voltage controlled oscillator and the digital to analog converter unit; and
performing a de-digitizing oreration on the modulated received signal with the digital to analog converter and the obtained sampling frequency.